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LOCAL BUS CONTROL PLD DESCRIPTIONS
module
iopld2;
flag
'-r3';
title
'eprom/io
wait
state
timer
and
bus
cycle
tracking'
"This
P2BR6
determines
the
number
of wait
states
and
recovery
"states
for
1/0
reads,
1/0
writes,
eprom
reads,
and
Interrupt
"ackn.wledge
cycles.
Choose
the
number
of
wall
slales
for
each
"peripheral
by
Ihe
chip
selects
U8
device
'p20r8';
h,I,c,x·I,O,.C.,.X.;
oe
pin
13;
cI
k 2
pin
1 ;
"80386
CLK2
clk
pin
2 ;
lor
d
pin
3 ;
lowr
pin
4 ;
eprd
pin
5 ;
In
t a
pin
6 ;
recv
pin
7 ;
ads
pin
8 ;
ready
pin
9 ;
cslws
pin
1 ° ;
cs3ws
pin
11
;
csSws
pin
14;
IIlIcnlO
pin
22;
wlcntl
pin
21
;
wtcnt2
pin
20
;
tlmedly
pin
15
;
alelo
pin
16
;
buscyc
pin
17
;
plpecyc
pin
18
;
I
die
•
[1,
1 , 1 , 1 ]
I
1m
e 1 •
[1,
1 , 1 , 0 ]
Ilme2'
[1,1,0,1]
Ilme3'
[1,1,0,0]
tlme4'
[1,0,1,1]
limeS'
[1,0,1,0]
tlme6'
[1,0,0,1]
Ilme7'
[1,0,0,0]
tlmeup'
[0,1,1,1]
low
low
low
low
low
low
low
low
from
fro
m
from
"wall
"walt
"wall
"time
"high
II
1
ow
"low
during
phase
I,
high
during
p ha H
to
read
10
to
w r I t e
10
10
read
eproms
for
Interrupt
acknowledge
during
flo
at
and
recovery
to
begin
bus
cycles
to
end
bus
cycles
decoder:
1
wa
It
s I
ate
chi
p
select
decoder:
3
wa
It
5
ta
t e
chi
p
Hlecl
decoder:
5
wall
5
ta
I e
chi
p
selecl
stat
e
counter
b I I
state
counter
b I I
stale
counter
b I I
delay
output
to
make
address
latch
transparent
during
active
b u 5
cycles
a
fie
r
pipellned
bU5
cycles
2
"""""""""11""1111"""
""IIIIII"""IIII""""nllll""""IIIIII""""""IIIIII"""""II""
"10
address
lalch
enable
equations
!alelo
:.
(!Iord
clk)
(!Iowr
clk)
(!Inta'
clk)
,
(!alelo.
!clk);
II""""IIUIIIIIIIIII""""IIIIII""""""""""IIIIIIIIII""IIIIII"II""""""'I""""""lllllIn
Figure A-2. IOPLD2 Equations
A-6