8Kx8
8Kx8
8Kx8
CACHE
SRAM
(8Kx
8)
CACHE SUBSYSTEMS
<t
!;:
C
CIl
~~~~----------~~
4x245
...J
OATA
1
.1U-L---'\IA
SIJL---I--''\
~
CSO#-
CS3#
WEI
00-031
~
4
CALEN
CT/R#
COEA#
CSO#-CS3#
Figure 7-14. Direct Mapped Cache with Data Buffers
4Kx4
CACHE
SRAM
BANK
A
(4Kx4)
ADDRESS
CACHE
SRAM
BANK
B
(4K,32)
DATAI¢========+~
00-031
CALEN
CWEA#
COEA#
CSO#-CS3#
CWEB#
COEB#
82385
CACHE
CONTROL
82385
CACHE
CONTROL
Figure 7-15. Two-Way Set Associative Cache without Data Buffers
7-21
231732;7-14
231732;7-15