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DRAM PLD DESCRIPTIONS
module
DRAM_CONTROLLER_FOR_80386
flag
'-r3','-t2
U
title
'80386
Interleaved
DRAM
Controller
pal-t
plpellned
lws'
U33
device
'P20R8';
"
Constants:
ON
OFF
h
I
1 ;
o ;
1 ;
o ;
• X • ; "
ABEL
'don't
care'
symbol
• C • ;
"
ABEL
'clacking
Input'
symbol
"Pin
names:
"Control
c
lk
2
oe
pin
1;
"81il386
Double-Frequency system
clock
pin
13;
"Output
Enable
(tie
active
law>
"Inputs
pc
lk
ads
mlo
pa2
Iready
r a
sOp
5e
11
raslp
ref
I n
res
e t
s e 12
"Outputs
r a s 0
r a s 1
rowsel
muxoe
dramstar(
refadroe
plpecyc
buscyc
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
I
die
startdram
•
cal_den'
coLden2-
2 ;
3 ;
4 ;
5 ;
6 ;
7 ;
S;
8 ;
1 0 ;
11
;
14;
17
;
18
;
20
;
1
S;
15
;
16
;
21
;
22;
rasOldle'
[II;
raslldle'
[II;
rasOact
•
[01;
ras1act·
[01;
"processor/phase
c
lack
"ads
from
80386
"M/IO
from
80386
"A2 from
80386
lIinver5e
of
Ready In t a
the
80386
"RASO
precharged
from
PLD2
"High
for
DRAM
address
"RASI
precharged
fro
m
PLD
2
"request
for
s
tar
t
refresh
"
RESET
from c
lac
k
circuitry
"
High
for
DRAM
address
cycles
"DRAM
RAS
aut
put
for
bank 0
"DRAM
RAS
output
for
bank
1
"DRAM
address
mux
s e I e c t
"DRAM
address
mux
output
enable
"DSTART
for
PLD2
and
refresh
"
output
enable
for
refresh
"
law
during
pipe
cycle
"
law
[1,1)
;
[ 0 , 1 ) ;
[ 0 , 0 I ;
[ 1 , 0 I ;
when
bus
cycle
active
e q •
address
select·
[5ell
&
sel21
;
PLD
1,"""'IU"""""""""""""""""'I""""'I"""""IIII""""'1111'"""""""'1""'11111111'"""'1
Figure B-2. DRAMP1 PLD Equations
8-2