I/O INTERFACING
ADDRESS =[]s
LINE
iORC
iiD .
110
DEVICE
.
iOWC
WR
A15
A14
(AlONE
CHIP SELECT
CS
CS
iiD
--C
WIi
CS
cs
iiD
WR
(B) MULTIPLE CHIP SELECTS
110
DEVICE
1/0 DEVICE
Figure 8-2. Linear Chip Selects
231732iB-2
The bus interface control logic presented here
is
identical to the one used
in
the basic
memory interface described in Chapter
6.
In most systems, the same control logic,
address latches, and data buffers can be used to access both memory and
I/O devices.
The schematic of the interface
is
shown in Figure
8-4
and described in the following
sections.
8.3.1
Address Latch
Latches maintain the address for the duration of the bus cycle. In this example,
74x373
latches are used.
The
74x373
Latch Enable (LE) input
is
controlled
by
the Address Latch Enable (ALE)
signal from the bus control logic that goes active at the start of each bus cycle. The
74x373
Outp:ut Enable
(OE#)
is
always active.
8.3.2 Address Decoder
In this example, the address decoder, which converts the Inte1386
DX
microprocessor
address into chip-select signals,
is
located before the address latches. In general, the
decoder may also be placed after the latches.
If
it
is
placed before the latches, the
8-5
