I/O INTERFACING
I
BUS
ADDRESS
I
~
CONTROL
t--
,..-l\
DECODER
LOGIC
WAIT-BTATE
I-
GENERATOR
rV
-"
110
DEVICE
~
#1
-
-
-,I
ADDRESS
BUS
.~
LATCH
READY.
STATUS
r
I-
:.....
ADDRESS
J..
110
i3B6'·
OX
CPU
DEVICE
~
112
DATA
~
A
-".
TRANSCEIVER
V"
DATA
....
..
...
..
231732i8-3
Figure 8·3. Basic I/O Interface
Block
Diagram
chip-select signal becomes valid
as
early
as
possible but must be latched along with the
address. Therefore, the number of address latches needed
is
determined
by
the location
of the address decoder
as
well
as
the number of address bits and chip-select signals
required by the interface. The chip-select signals are routed to the bus control logic to
set the correct number of wait states for the accessed device.
The decoder consists of two one-of-four decoders, one for memory address decoding and
one for
I/O address decoding. In general, the number of decoders needed depends on
the memory mapping complexity.
In
this basic example, an output of the memory
address decoder activates the
I/O address decoder for I/O accesses. The addresses for
the
I/O devices are located
so
that only address bits A4 and
AS
are needed to generate
the correct chip-select signal.
8.3.3 Data Transceiver
Standard 8-bit transceivers
(74x24S,
in this example) provide isolation and additional
drive capability for the Inte1386 DX microprocessor data bus. Transceivers are necessary
to prevent the contention on the data bus that occurs if some devices are
slow
to remove
read data from the data bus after a read
cycle.
If
a write
cycle
follows a read cycle; the
Intel386 DX microprocessor
may
drive the data bus before a
slow
device has removed its
outputs from the bus, potentially causing bus contention problems. Transceivers can be
omitted only if the data float time of the device
is
short enough and the load on the
Intel386 DX microprocessor data pins meets device specifications.
8-6
