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MUL TIBUS I AND Intel386 DX MICROPROCESSOR
Each processing subsystem contains its own
82289
Bus Arbiter. The Bus Arbiter directs ,
its processor onto the bus and allows higher and lower priority bus masters to access the
bus.
Once the bus arbiter gains control of MULTIBUS I, the Inte1386 DX microproces-
sor can access system resources. The bus arbiter handles bus contention in a manner that
is
transparent to the Intel386 DX microprocessor.
Each processor in the multiprocessing system initiates bus cycles
as
though it has exclu-
sive
use of MULTI BUS
I.
The bus arbiter keeps track of whether the subsystem has
control of the bus and prevents the bus controller from accessing the bus when the
subsystem does not control the bus.
When the bus arbiter receives control
of
MULTIBUS
I,
it enables the bus controller and
address latches to drive MULTI
BUS
I.
When the transfer
is
complete, MULTIBUS I
returns the XACK# signal, which activates READY # to end the bus
cycle.
9.4.1 Priority Resolution
Because a
MUt
TIBUS I system includes many bus masters, logic must be provided
to resolve priority between two bus masters that simultaneously request control of
MULTIBUS
I.
Figure
9-7
shows two common methods for resolving priority: serial
priority and parallel priority.
~
The serial priority technique
is
implemented
py
daisy-chaining the Bus Priority In
(BPRN#) and Bus Priority
Out
(BPRO#)
signals of all the bus arbiters
in
the system.
Due to delays in the daisy chain, this technique accommodates only a limited number of
bus arbiters.
The parallel priority technique requires external logic to recognize the
BPRN # inputs
from all bus arbiters and return the
BPRO#
signal
aCtive
to the requesting bus arbiter
that has the highest priority. The number of bus arbiters accommodated with this tech-
nique depends on the complexity of the decoding logic.
Priority resolution logic need not be included in the design of a single processing sub-
system with a
MULTIBUS I interface. The bus arbiter takes control of MULTIBUS I
when the
BPRN#
signal goes active and relinquishes control when
BPRN#
goes inac-
tive. As
long.as external logic exists to control the
BPRN#
inputs
of
all bus arbiters, a
subsystem can be designed independent of the priority resolution circuit.
9.4.2 82289 Operating Modes
Following a MUL TIBUS I cycle, the controlling bus arbiter can either retain bus control
or release control
so
that another bus master can access the bus. Three modes for
relinquishing bus control are
as
follows:
• Mode
1-
The bus arbiter releases the bus at the end of each
cycle.
• Mode 2 - The bus arbiter retains control of the bus until another bus master (of any
priority) requests control.
• Mode 3 - The bus arbiter retains control of the bus until a higher priority bus master
requests control.
9-11