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INTERNAL ARCHITECTURE
2.4 EXECUTION UNIT
The Execution Unit executes the instructions from the Instruction Queue and therefore
communicates with all other units required to complete the instruction. The functions of
its three subunits are
as
follows:
• The Control Unit contains microcode and special parallel hardware that speeds
mul~
tiply, divide, and effective address calculation.
• The Data Unit contains the ALU, a file of eight 32-bit
general~purpose
registers, and
a 64-bit barrel shifter (which performs multiple bit shifts in one clock). The Data Unit
performs data operations requested
by
the Control Unit.
• The Protection Test Unit checks for segmentation violations under the control of the
microcode.
To speed up the execution of memory reference instructions, the Execution Unit par-
tially overlaps the execution of any memory reference instruction with the previous
instruction. Because memory reference instructions are frequent, a performance gain of
approximately nine percent
is
achieved.
2.5 SEGMENTATION UNIT
The Segmentation Unit translates logical addresses into linear addresses at the request
of the Execution Unit. The on-chip
Segment Descriptor Cache stores the currently used
segment descriptors to speed this translation. At the same time it performs the transla-
tion, the Segmentation Unit checks for bus-cycle segmentation violations. (These checks
are separate from the static segmentation violation checks performed
by
the Protection
Test Unit.) The translated linear address
is
forwarded to the Paging Unit.
2.6 PAGING UNIT
When the Intel386 DX microprocessor paging mechanism
is
enabled, the Paging Unit
translates linear addresses generated
by
the Segmentation Unit or the Code Prefetch
Unit into physical addresses. (If paging
is
not enabled, the physical address
is
the same
as
the linear address, and no translation
is
necessary.) The Page Descriptor Cache stores
recently used
Page Directory and Page Table entries in its Translation Lookaside Buffer
(TLB) to speed this translation. The
Paging Unit forwards physical addresses to the Bus
Interface Unit to perform memory and
I/O accesses.
2-4