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CACHE
SUBS,YSTEMS
•
Data
Hold Time (Without Buffers)
The smaller
of:
1xCLK2 +
386
Min
Data
-
385
CWE#
Max
Period Hold (t22) Delay (t22a)
1xCLK2
+
386
Min
Data
-
385
CWE#
Max
Period Valid (t12) Delay (t22a)
7.7.4 System Interface
The
82385
presents the 82385 local bus for the system interface. Since the 82385 local
bus
is
functionally equivalent to the Intel386
DX
microprocessor local bus,
the'
system
interface
is
virtually identical. There are some timing differences that need to
be
under-
stood. These relate to the data setup time and the ready setup time.
7.7.4.1
READ
DATA SETUP
At
33
MHz, the read data setup time for the Inte1386
DX
microprocessor
is
5 ns. This
does not take into account any buffers in the data path which add to the
setup~With
an
82385
cache system, the need to update the cache memory for read miss cycles changes
the data setup. The equation to determine the data setup for the buffered cache orga-
nization
is
given
by:
74xx646
Max Propagation Delay +
74xx245
Max Propagation Delay
+ SRAM Min Write Setup + One CLK2 Period - 82385
CWE#
Min Delay
(82385 t22a)
The BREADY # signal
is
used
by
the
82385
to determine when the cache update can
be
completed for a read-miss cycle. When
BREADY
#
is
activated at the end
of
a cache-
read miss access, it tells the 82385 to trigger the rising edge
of
CWE#
which updates the
cache-data SRAMs.
For
this reason, the
BREADY#
setup (82385 t37a) for a cache-
read miss
is
13
ns at
33
MHz.
7.7.5 Special Design Notes
The ability to disable the cache
is
useful for system memory diagnostic purposes. While
the
82385
itself does not have a specific cache enable/disable feature, the FLUSH input
can effectively
be
used to disable the cache.
By
keeping the FLUSH input active, all
Inte1386
DX
microprocessor memory accesses (which have
LBA#
inactive) will
be
for-
warded to the system bus. The FLUSH pin invalidates all
of
the directory tags which
makes the cycles read misses.
In
addition, no coherency issues will exist when the cache
is
enabled since it was previously flushed.
Certain architectures which
use the Intel386
DX
microprocessor implement a special
, function for the A20 address line. When the Intel386
DX
microprocessor
is
running in
Real
Mode,the
A20 line
is
kept active
low
(via a registered I/O poit)
so
that regardless
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