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CLOCK
GENERATOR
CLK2
1386"
OX
MICRO·
PROCESSOR
CACHE
MEMORY
SYSTEM OVERVIEW
1387'·
OX
MATH
COPROCESSOR
82835
CACHE
CONTROLLER
MAIN
MEMORY
PERIPHERALS
82370
OMA
82596
OX
LAN
COPROCESSOR
Figure 1-1.
l"ntel386™
OX
Microprocessor System Block Diagram
231732i1-1
in detail in Chapter
2.
Because the Intel386
DX
microprocessor prefetches instructions
and queues them internally, instruction fetch and decode times are absorbed in the
pipeline; the processor rarely has to wait for an instruction to execute.
Pipelining
is
not unusual in modern microprocessor architecture; however, including
the memory management unit (MMU) in the on-chip pipeline
is
a unique feature of the
Intel386
DX
Architecture.
By
performing memory management on-chip, the
Intel386 DX microprocessor eliminates the serious access delays typical of implementa-
tions that use off-chip memory management units. The benefit
is
not only high perfor-
mance but also relaxed memory-access time requirements, hence lower system cost.
1-2