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ClK2
ClK
BEO#-BE3#,
A2-A31,
M/IO#, DIC#
W/R#
AD5#
NA#
B516#
READY#
lOCK#
IDLE
TI
LOCAL BUS INTERFACE
CYCLE 1
NON·PIPELINED
(READ)
T1
T2
T1
CYCLE 2
NON·PIPElINED
(READ)
T2
VALID 2
IDLE
T2
n
DO-D31
-
---
--,-
-
--0--
I
Figure 3-8. Non-Pipelined Address Read Cycles
231732i3·8
• At the end of T2,
READY#
is
sampled.
If
READY#
is
low,
the Inte1386
DX
micro-
processor reads the input data on the data bus.
•
If
READY#
is
high, wait states (one CLK cycle) are added until
READY#
is
sam-
pled
low.
READY#
is
sampled at the end of each wait state.
• Once READY #
is
sampled
low,
the Inte1386
DX
microprocessor reads the input
data, and the read
cycle
terminates.
If
a new bus cycle
is
pending, it begins on the
next CLK cycle.
3-12