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CHAPTER 5
COPROCESSOR HARDWARE INTERFACE
A numeric coprocessor enhances the performance of an Inte1386
DX
microprocessor
system
by
performing numeric instructions in parallel with the Inte1386 DX microproces-
sor. The Inte1386
DX
microprocessor automatically passes on these instructions to the
coprocessor
as
it encounters them.
The Intel387 DX math coprocessor performs 32-bit data transfers and interfaces directly
with the Intel386
DX
microprocessor. The Inte1387
DX
math coprocessor supports the
instruction set
of
both the 80287 and the 8087, offering additional enhancements that
include full compatibility with the
IEEE
Floating-Point Standard, 754-1985. The perfor-
mance of a 16-MHz Intel387
DX
math coprocessor
is
about eight times faster than that
of a 5-MHz
80287.
The Intel386
DX
microprocessor samples its
ERROR#
input during initialization to
determine if a coprocessor
is
present. Very little logic or board space
is
required to
support a numerics option. The math coprocessor can be an option. A socket can be
designed on the board such that the Intel387
DX
math coprocessor is a user installed
option.
Data
transfers to and from a coprocessor are accomplished through I/O addresses
800000F8H and 800000FCH; these addresses are automatically generated
by
the
Inte1386
DX
microprocessor for coprocessor instructions and allow simple chip-select
generation using A31 (high) and
M/IO#
(low). Because
A31
is
high for coprocessor
cycles, the coprocessor addresses lie outside the range of the programmed
I/O address
space and are easy to distinguish from programmed
I/O addresses. Coprocessor usage
is
independent of the I/O privilege level
of
the Intel386
DX
microprocessor.
The Intel386
DX
microprocessor has three input signals for controlling data transfer to
and from an Intel387
DX
math coprocessor: BUSY#, Processor Extension Request
(PEREQ), and
ERROR#.
These signals, which are level-sensitive and may be asynchro-
nous to the CLK2 input of the Inte1386
DX
microprocessor, are described as follows:
• BUSY # indicates that the coprocessor
is
executing an instruction and therefore can-
not accept a new one. When the Intel386
DX
microprocessor encounters any copro-
cessor instruction except FNINIT and FNCLEX, the
BUSY # input must be inactive
(high) before the coprocessor accepts the instruction. A new instruction therefore
cannot overrun the execution of the current coprocessor instruction. (Certain
Inte1387
DX
math coprocessor instructions can be transferred when BUSY #
is
active
(low). These instructions are queued and do not interfere with the current
instruction. )
•
PEREQ
indicates that the coprocessor needs to transfer data to
or
from memory.
Because the coprocessor
is
never a bus master, all input and output data transfers are
performed
by
the
Intel386
DX
microprocessor.
PEREQ
always goes inactive before
BUSY # goes inactive.
5-1