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LOCAL BUS INTERFACE
• Saving the Flags register and CS:EIP registers (which contain the return address)
requires time.
•
If
interrupt servicing requires a task switch, time must· be allowed for saving and
restoring registers.
•
If
the interrupt service routine saves registers that are not automatically saved by the
Intel386
DX
microprocessor, these instructions also delay the beginning of interrupt
servicing.
The longest latency occurs when the interrupt request arrives while the Intel386
DX
microprocessor
is
executing a long instruction such
as
multiplication, division, or a task-
switch in the Protected mode.
If
the instruction loads the Stack Segment register, an interrupt
is
not processed until
after the following instruction, which should be an ESP load. This allows the entire stack
pointer to be loaded without interruption.
If
an instruction sets the interrupt flag (thereby enabling interrupts), an interrupt
is
not
processed until after the next instruction.
3.5
BUS
LOCK
In a system in which more than one device may control the local bus, locked cycles must
be used when it
is
critical that two or more bus cycles follow one another immediately.
Otherwise, the cycles can be separated
by
a cycle from another bus master.
Any
bus cycles that must be performed back-to-back without any intervening bus cycles
by
other bus masters should be locked. The use of a semaphore
is
one example of this
precept. The value
of
a semaphore indicates a condition, such
as
the availability of a
device.
If
the Inte1386 DX microprocessor reads a semaphore to determine that a device
is
available, then writes a new value to the semaphore to indicate that it intends to
take control of the device, the read cycle and write cycle should be locked to prevent
another bus master from reading from
or
writing to the semaphore in between the two
cycles. The erroneous condition that could result from unlocked cycles
is
illustrated in
Figure 3-18.
The
LOCK#
output of the Intel386
DX
microprocessor signals the other bus masters
that they may not gain control of the bus.
In
addition, an Intel386
DX
microprocessor
with
LOCK#
asserted
will
not recognize a
HOLD
request from another bus master.
3.5.1 Locked Cycle Activators
The
LOCK#
signal
is
activated explicitly by the LOCK prefix on certain instructions.
LOCK#
is
also asserted automatically for an XCHG instruction, a descriptor update,
interrupt acknowledge cycles, and a page table update.
3-30