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COPROCESSOR HARDWARE INTERFACE
Two,
three, four or
five
bus cycles may be necessary for each operand transfer. These
cycles include one coprocessor cycle plus one
of
the following:
• One memory cycle for an aligned operand
• Two memory cycles for a misaligned operand
• Two
Or
three memory cycles for misaligned 32-bit operands to 16-bit memory
• Four memory cycles for misaligned 64-bit operands to 16-bit memory
Data
transfers for the coprocessor have the same bus priority
as
programmed data
transfers.
5.3 80287/lnte1387
OX
MATH COPROCESSOR RECOGNITION
In
systems that provide a math coprocessor, it
is
necessary for both hardware and soft-
ware to correctly determine the presence and identity of the coprocessor.
5.3.1 Hardware Recognition of the NPX
The Intel386
DX
microprocessor samples its
ERROR#
input some time after the falling
edge of RESET and before executing the first ESC instruction. The Intel387
DX
math
coprocessor keeps its
ERROR#
output in active state after hardware reset. Subse-
quently if
ERROR#
was sampled active, the Intel386
DX
CPU employs the 32-bit
protocol
of
the Intel387
DX
math coprocessor.
5.3.2 Software Recognition of the NPX
Figure
5-3
shows an example of a recognition routine that determines whether a math
coprocessor
is
present, and distinguishes between the Intel387 SX/DX coprocessors and
the
8087/80287. This routine can be executed on any Intel386 DX, Inte1386 SX, 80286, or
8086 microprocessor hardware configuration that has a math coprocessor socket.
Even though the Intel386
DX
microprocessor uses the value
of
ERROR#
after RESET
to select microcode which conforms to the Inte1387
DX
32-bit protocol, the software
designer should not use Intel reserved bits to determine the presence or identity of
coprocessors. To assure compatibility with future processors a software recognition test
is
necessary.
The
example guards against the possibility of accidentally reading an expected value
from a floating data bus when no math coprocessor
is
present. Data read from a floating
bus
is
undefined.
By
expecting to read a specific bit pattern from the math coprocessor,
the routine protects itself from the indeterminate state of the bus. The example also
avoids depending
on
any values in reserved bits, thereby maintaining compatibility with
future numerics coprocessors.
5-6