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M/IO#
D/C#
Low Low
Low Low
Low High
Low High
High Low
High
Low
High
High
High High
INTERNAL
PROCESSOR CLOCK
(CLK)
lOCAL
BUS INTERFACE
Table
3-2. Bus Cycle Definitions
W/R#
Low
High
Low
High
Low
High
Low
High
Bus
Cycle
Type
INTERRUPT ACKNOWLEDGE
does not occur when
ADS#
is
low
I/O
DATA
READ
I/O DATA
WRITE
INSTRUCTION FETCH
HALT:
SHUTDOWN:
Address = 2 Address = 0
(BEO#
High (BEO# Low
BE1#
High BE1# High
BE2#
Low BE2# High
BE3#
High
BE3# High
A2-A31 Low) A2-A31
Low)
MEMORY DATA
READ
MEMORY DATA WRITE
PROCESSOR CLOCK
PERIOD
PROCESSOR CLOCK
PERIOD
Locked?
Yes
-
No
No
No
No
Some Cycles
Some Cycles
CLK2 PERIOD CLK2 PERIOD CLK2 PERIOD CLK2 PERIOD
<1>1
<1>2
<1>1
<1>2
62 ns MIN
80386·16
(16 MHz MAX)
50 ns MIN
·
80386-20
(20
MHz MAX)
40 ns MIN
·
80386-25
(25 MHz MAX)
30 ns MIN
·
80386-33
(33 MHz MAX)
231732i3-1
Figure 3-1.
ClK2and
ClK
Relationship
3-4