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MULTIBUS I AND Intel386
DX
MICROPROCESSOR
Inverting address latches convert the
Inte1386
DX microprocessor address outputs to the
active-low
MULTIBUS I address bits. MULTIBUS I address bits are numbered in
hexadecimal
so
that
A23-AO
on the Intel386
DX
microprocessor bus become
ADR17#-ADRO# on the
MULTI
BUS
I (as shown in Figure 9-4). The
BHE#
signal
is
latched to provide the MULTIBUS I
BHEN#
signal.
MUL TIBUS I requires address outputs to be valid for at least
50
nanoseconds after the
MULTIBUS I command goes inactive; therefore, the address on
all
bus cycles
is
latched.
The Address Enable
(AEN#)
output of the
82289
Bus Arbiter, which goes active when
the
82289
has control of the MULTIBUS I,
is
an output enable for the MULTIBUS I
latches. The
ALE#
output of the
82288
latches the
Inte1386
DX microprocessor address
for the
MULTIBUS I,
as
shown in Figure
9-2.
Inverting latch/transceivers are needed to provide active-low MULTIBUS I data bits.
MULTIBUS I data bits are numbered in hexadecimal,
so
D1S-DO
convert to
DATF#-
DATO#. Data
is
latched only on write
cycles.
For MULTIBUS I write
cycles,
the
82288
ALE#,
DEN, and
DT/R#
inputs can control the address latches and data latch/ trans-
. ceivers. For MUL TIBUS I read
cycles,
the local bus
RD#
signal can control the latch/
transceivers.
If
DEN
were used, data contention on the Intel386
DX
microprocessor
local bus would result when a
MULTIBUS I read
cycle
immediately followed a local
write,
cycle.
ADDRESS
A23-AO
INVERTING
LATCH
ALE----'
(FROM
82288)'
INVERTING
LATCHI
TRANSCEIVER
DEN---'
DTIRH
.:.-----'
(FROM
82288)
Figure 9·2. MULTIBUS I Address Latches and Data Transceivers
9-4
231732i9-2