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MUL TIBUS I AND Intel386
OX
MICROPROCESSOR
SERIAL PRIORITY RESOLVING TECHNIQUE
74146
PRIORITY
4 ENCODER
PARALLEL PRIORITY RESOLVING TECHNIQUE
Figure 9-7. Bus Priority Resolution
1
74136
;
3T06
DECODER 4
231732i9-7
In addition, the bus arbiter can switch between modes 2 and
3,
based on the type
of
bus
cycle.
Figure
9-8
shows the strapping configurations required to implement each of these four
techniques.
The operating mode of one bus arbiter affects the throughput of both the individual
subsystem as well
as
other subsystems on MUL TIBUS
I.
This
is
because the delay
required to transfer
MUL TIBUS I control from one bus arbiter to another affects all
9-12