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TEST CAPABILITIES
31
12
11
5 4
o '
~------------~--~~~~~
31
LINEAR
ADDRESS
PHYSICAL
ADDRESS
TAG
COMMAND
REGISTER
LOOKUP/
WRITEN
12
11
5 4 3
2 1
0
~I
DATA
REGISTER
MIT/REPLACEMENT
MISS
POINTER
OR
REPLACEMENT
BIT
Figure 12-2. TLB Test Registers
231732i12-2
The complement of the Dirty, User, and Writable bits are provided to force a hit or miss
for TLB lookups. A lookup operation with a bit and its complement both low
is
forced to
be a miss; if both bits are high, a hit
is
forced. A write operation must always be per-
formed with a bit and its complement bit having opposite values.
The data register has the format shown in Figure
12-2
(bottom). The replacement
pointer indicates which of the four sets of the TLB
is
to receive write data. Its value
is
changed according to a proprietary algorithm after every TLB hit. For testing, a TLB
write may use the replacement pointer value that exists in the TLB, or it may use the
value in bits 3 and 2 of the data register.
If
data register bit 4 =
0,
the existing replace-
ment pointer
is
used.
If
bit 4 =
1,
bits 3 and 2 of the data register are used.
The TLB write operation progresses
as
follows:
1.
The physical address, replacement bit, and replacement pointer value (optional) are
written to the data register.
2.
The linear address and tag values are written to the command register,
as
well
as
a
o value for bit
O.
It
is
important not to write the same linear address to more than one TLB entry. Oth-
erwise, hit information returned during a TLB lookup operation
is
undefined.
12-4