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APPENDIX A
LOCAL
BUS CONTROL PLD DESCRIPTIONS
The bus controller
is
implemented in two PLDs. One PLD (called IOPLD1) follows the
Intel386
DX
microprocessor status lines and initiates I/O and
EPROM
accesses. The
second
PLD (IOPLD2) contains the bus cycle tracking state machine and determines the
number of wait states for
I/O system accesses.
EPROMs and peripherals are usually arranged with 16-bit data bus interfaces. This
subsystem asserts BS16# for all accesses to the
I/O and EPROMs. Because all accesses
are BS16#, pipelined cycles cannot
be
requested. This system can coexist with a
subsystem that uses pipelining, provided the pipelined system keeps
NA#
asserted until
the end
of
the cycle. The DRAM subsystem described in Chapter 6
will
meet this
requirement.
The
PLDs are clocked
by
CLK2. They could also be clocked by CLK. Using CLK2 has
the following advantages over using CLK:
• The skew from clock to command signal
is
reduced,
so
higher performance
is
possible
with slower devices.
• The Inte1386
DX
microprocessor
ADS#
and
READY
# signals can
be
sampled
directly.
• The PLD can provide delays in
25
nanosecond, rather than
50
nanosecond,
increments.
The advantages of using CLK to clock the
PLDs are
as
follows:
• A slower PLD device could be used.
• One PLD input
is
saved because only CLK, rather than CLK and CLK2,
is
needed.
Because CLK2
is
used to clock the PLDs, the choice of PLDs
is
limited
by
the frequency
of the processor.
IOPLD1 FUNCTIONS
IOPLDl
is
implemented
as
two state machines. The first state machine enables the data
transceivers between the processor and the peripherals. The transceivers remain active
until the end
of
the bus cycle. The second state machine determines the type of cycle
that has been initiated.
Once a cycle has been started, the state machine waits for the
TIMEDLY # signal from
IOPLD2 before continuing the cycle.
IOPLD2 FUNCTIONS
The IOPLD2 has two functions. First, the PLD contains the bus cycle tracking state
machine. The BUSCYC# signal
is
used
by
IOPLDl
for determining the start of bus
cycles. Second, the
PLD counter determines the number of wait states from
IOPLDl
initiating a bus cycle until the time it returns TIMEDL Y # to
IOPLDl.
If
peripheral
A-1