Intel 386 Computer Hardware User Manual


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TABLE OF CONTENTS
Page
3.6.1
HOLD/HLDA Timing ................................................................................. .................. 3-33
3.6.2
HOLD Signal Latency·............................................ .................................................... 3-34
3.6.3
HOLD State Pin Conditions ............................................ ...... .................. ................... 3-35
3.7
RESET ........................................................................................................................... 3-35
3.7.1
RESET Timing ............................................................................................................ 3-35
3.7.2
Intel386
DX
Microprocessor Internal States .............................................................. 3-35
3.7.3
Intel386
DX
Microprocessor External States ............................................................. 3-36
CHAPTER 4
PERFORMANCE CONSIDERATIONS
4.1
WAIT STATES AND PIPELINING ............................................................................ :.......
4-1
CHAPTER 5
COPROCESSOR HARDWARE INTERFACE
5.1
Intel387
DX
MATH COPROCESSOR INTERFACE ......................................................... 5-2
5.1.1
Intel387
DX
Math Coprocessor Connections .............................................................. 5-2
5.1.2
Intel387
DX
Math Coprocessor Bus Cycles ................................................................ 5-4
5.1.3
Intel387
DX
Math Coprocessor Clock Input ............................................................... 5-4
5.2
LOCAL BUS ACTIVITY WITH THE Intel387
DX
MATH
COPROCESSOR ...................... 5-5
5.3
80287/lnte1387
DX
MATH COPROCESSOR RECOGNITION ........................................ 5-6
5.3.1
Hardware Recognition of the
NPX
.............................................................................. 5-6
5.3.2
Software Recognition of the
NPX
................................................................................ 5-6
CHAPTER 6
MEMORY
INTERFACING
6.1
MEMORY SPEED VERSUS PERFORMANCE AND COST ............................................
6-1
6.2 BASIC MEMORY INTERFACE ........................................................................................
6-1
6.2.1
TIL
Devices ................................................... ............................................................. 6-2
6.2.2
PLD
Devices ................................................................................................................. 6-3
6.2.3 Address Latch .............................................................................................................. 6-6
6.2.4 Address Decoder ......................................................................... ................................ 6-6
6.2.5 Data Transceiver .......................................................................................................... 6-7
6.2.6 Bus
Control Logic ........................................................................................................ 6-7
6.2.7
EPROM Interface ................................................................................................. ........ 6-9
6.2.8 16-Bit
Interface ...........................................................................................................
6-11
6.3 DYNAMIC
RAM
(DRAM)
INTERFACE ........................................................................... 6-12
6.3.1
Interleaved Memory .............................................................................................. ,.... 6-12
6.3.2
DRAM
Memory Performance ..................................................................................... 6-13
6.3.3
DRAM
Controller ........................................................................................................ 6-14
6.3.3.1 3-CLK
DRAM
CONTROLLER ............ .............. .................................... .................... 6-14
6.3.3.2
DRAM
TIMING ANALYSIS ............... :...................................................................... 6-19
6.3.3.3
LOGIC DELAY ......................................................................................................... 6-20
6.3.3.4
ADDRESS BUS TIMINGS ....................................................................................... 6-20
6.3.3.5
DATA
BUS TIMINGS ............................................................................................... 6-22
6.3.3.6
AVOIDING DATA BUS CONTENTION .............................................. :.....................
6~23
6.3.3.7 CONTROL SIGNAL TIMINGS ................................................................................. 6-24
6.3.3.8
LOGIC
PATHS
........................................................................................................ 6-25
6.3.3.9
CAPACITIVE LOADING ........................................................................................... 6-26
6.3.4
DRAM
Design Variations ........................................................................................... 6-26
6.3.4.1 3-CLK
DESIGN VARIATIONS .................................................................................. 6-26
6.3.4.2
USING TAP DELAY LINES ..................................................................................... 6-27
6.3.4.3
REDUCING THE CLOCK FREQUENCy................................................................. 6-27
6.3.5 Refresh
Cycles ....................................... ............. ....................................................... 6-28
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