CACHE SUBSYSTEMS
31
24 23
2 1 0
32-BIT I CACHE/DRAM I I +- BYTE
PROCESSOR
SELECT TAG ENABLE
ADDRESS
_ _
TAG
~
22 BITS
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000000
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16339C
FFFFF8
....
L...
___
'"
2816
BIT
SRAM
1_16
MEGABYTE
DRAM
~
24
BITS_I
DATA
24682468
DATA
~
11223344
4 BYTES
-
33333333
24682468
-
12345678
-
33333333
-
87654321
87654321
11223344
4096
BIT
SRAM
12345678
1-32BITS-t
16 MEGABYTE
DRAM
Figure 7-2. Fully Associative Cache Organization
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FFFFF8
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1633AO
16339C
163398
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231732i7-2
A fully associative cache provides the maximum flexibility in determining which blocks
are stored in the cache at any time. In the previous example, up to
128
unrelated blocks
could be stored in the cache. Unfortunately, a 128-address compare
is
usually unaccept-
ably slow, expensive, or both.
One
of
the basic issues of cache organization
is
how to
minimize the restrictions on which words may be stored in the cache while limiting the
number of required address comparisons.
7.2.2 Direct Mapped Cache
In a direct mapped cache, unlike a fully associative cache, only one address comparison
is
needed to determine whether requested data
is
in the cache.
The many address comparisons of the fully associative cache are necessary because any
block frem the main memory can be placed in any location of the cache. Thus, every
block of the cache must be checked for the requested address.
The
direct mapped cache
reduces the number of comparisons needed by allowing each block from the main
mem-
ory only one possible location in the cache.
7-4