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CHAPTER 7
CACHE
SUBSYSTEMS
Operating at
33
MHz, the Inte1386
DX
microprocessor can perform a complete bus cycle
in only
60
nanoseconds, for a maximum bandwidth of
66
megabytes per second. To
sustain this maximum speed, the Intel386
DX
microprocessor must be matched with a
high-performance memory system. The system must be fast enough to complete bus
cycles with no wait states and large enough to allow the Intel386 DX microprocessor to
execute large application programs.
Traditional memory systems have been implemented with dynamic RAMs (DRAMs),
which provide a large amount of memory for a small amount
of
board space and money.
However, low-cost DRAMs that can complete random read-write cycles
in
60
nanosec-
onds are not commonly available. Faster static RAMs
(SRAMs) can meet the bus timing
requirement, but they offer a relatively small amount
of
memory at a higher cost. Large
SRAM systems can be prohibitively expensive.
A cache memory system contains a small amount of fast memory
(SRAM) and a large
amount
of
slow memory (DRAM). The system
is
configured to simulate a large amount
of fast memory. Cache memory therefore provides the performance of
SRAMs at a cost
approaching that
of
DRAMs. A cache memory system (see Figure 7-1) consists of the
following sections:
..
Cache-fast
SRAMs between the processor and the (slower) main memory
..
Main
memory-DRAMs
..
Cache controller
-logic
to implement
the
cache .
r--------------------,
DRAM
SRAM
CACHE
1-
. MAIN
1386'·
OX
MEMORY
t
CACHE
CONTROLLER
L
____________________
~
CACH
E MEMORY
SYSTEM
Figure 7-1. Cache Memory System
7-1
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