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DRAM PLD DESCRIPTIONS
state_diagram
[cas,ale];
state
[1,1]:
if
(pclk
&
!rasO
&
ras1
&
!w_r)
then
[0,0]
else
if
(pclk
&
rasO
&
!ras1
&
!w_r)
then
[0,0]
else
if
(pclk
&
!rasO
&
ras1
&
w_r)
then
[1,0)
else
if
(pclk
&
rasO
&
!ras1
&
w_r)
then
[1,0)
else
[1,1);
state
[1,0]:
n
wait
fer
valid
write
data
gete
[0,0];
state
[0,0]:
if
(reset
&
pclk)
then
[1,1]
else
if
(pclk
&
!dramrdy)
then
[1,1]
else
[0,0];
state
[0,1):
"invalid
state
gote
[1,1];
Figure B-3. DRAMP2 PLD Equations (Contd.)
8-9