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LOCAL BUS INTERFACE
Once
NA#
is
sampled active, it remains active internally throughout the current bus
cycle.
If
NA#
and READY # are active in the same CLK cycle, the state of
NA#
is
irrelevant, because READY # causes the start of a new bus cycle; therefore, the new
address and status signals are always output regardless of the state of
NA#.
A complete discussion of the considerations for using address pipelining can be found in
the
386'"
DX
Microprocessor Data Sheet (Order Number 231630).
3.1.7 Interrupt Acknowledge Cycle
An unmasked interrupt causes the Intel386
DX
microprocessor to suspend execution of
the current program (after it completes the instruction it
is
executing) and perform
instructions from another program called an interrupt service routine. Interrupts are
described in detail in Section 3.4.
The 8259A Programmable Interrupt Controller
is
a system component that coordinates
the interrupts of several devices (eight interrupts for a single 8259A; up to
64
interrupts
with eight cascaded 8259As). When a device signals an interrupt request, the 8259A
activates the
INTR
input to the Inte1386
DX
microprocessor.
Interrupt acknowledge cycles are special bus cycles designed to activate the 8259A INTA
input. INTA signals the 8259A to output a service-routine vector on the data bus. The
Intel386
DX
microprocessor performs two back-to-back interrupt acknowledge cycles in
response to an active
INTR
input (as long
as
the interrupt flag of the Intel386
DX
microprocessor
is
enabled).
Interrupt acknowledge cycles are similar to regular bus cycles in that the Intel386
DX
microprocessor bus outputs signals
atthe
start of each bus cycle and an active READY #
terminates each bus cycle. The cycles are shown in Figure 3-1l.
•
ADS#
is
driven
low
to start each bus cycle.
• Control signals
M/IO#,
D/C#,
and
W/R#
are driven
low
to signal two interrupt-
acknowledge bus cycles. These signals must be decoded to generate the INTA input
signal for the 8259A. The decoding logic
is
usually included in the bus controller logic
for the particular design. Bus controller designs are discussed in Chapters 6 and
8.
•
LOCK#
is
active from the beginning of
the
first cycle to the end
of
the second.
HOLD
requests from other bus masters are not recognized until after the second
interrupt acknowledge cycle.
• The address driven during the first cycle
is
4;
during the second cycle, the address
is
O.
BE3#, BE2#,
and
BE1#
are high, BEO#
is
low,
and A31-A3 are
low
for both cycles;
A2
is
high for the first cycle and low for the second.
• The Intel386
DX
microprocessor floats D31-DO for both cycles; however, at the end
of
.the second cycle, the service routine
vector
at the 8259A outputs
is
read by the
Inte1386
DX
microprocessor on pins D7-DO.
• , READY # must
go
low
to terminate each cycle.
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