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TABLE OF CONTENTS
Figures
Title
Intel386™
DX
Microprocessor System Block Diagram ................................. .
Micro
Channel-Compatible Solution with
82311
Chip Set ........................... .
Instruction Pipelining ..................................................................................... .
Intel386™
DX
Microprocessor Functional Units ............................................ .
ClK2
and
ClK
Relationship .......................................................................... .
Intel386™
DX
CPU
Bus States Timing Example ...................................... : .... .
Bus
State Diagram (Does Not Include Address Pipelining) ......................... .
Non-Pipelined Address and Pipelined Address Differences ........................ .
Consecutive Bytes
in
Hardware Implementation .......................................... .
Address, Data Bus, and Byte
Enables for 32-Bit Bus ............ ; ....................
..
Misaligned Transfer ............................................... , ........................................ .
Non-Pipelined Address Read Cycles ............................................................ .
Non-Pipelined Address Write Cycles ............................................................ .
Pipelined Address Cycles .............................................................................. .
Interrupt Acknowledge Bus Cycles ............................................................... .
Internal
NA#
and
BS16#
logic
.................................................................... .
32-Bit and 16-Bit Bus
Cycle Timing .............................................................
;.
32-Bit and 16-Bit Data Addressing ................................................................ .
Using
ClK
to Determine Bus Cycle Start ..................................................... .
Clock Generator ............................................................................................. .
'ADS# Synchronizer ....................................................................................... .
Error Condition Caused by
Unlocked Cycles ............................................... .
lOCK#
Signal during Address Pipelining .................................................... .
Bus
State Diagram with HOLD State ............................................................ .
RESET,
ClK,
and
ClK2
Timing .................................................................... .
Intel386™
DX
CPU
System with Intel387'M
DX
Math Coprocessor .............. .
Pseudo-Synchronous
Interface ..................................................................... .
Software Routine to Recognize the Coprocessor ............................. : ........... .
Basic Memory
Interface Block Diagram ............................................ , ........... .
PlD
Equation arid Device Implementation ................................................... .
85C220,
EPlD
Macrocell Architecture ........................................................... .
I/O Controller Schematic ............................................................................... .
250 Nanosecond
EPROM
Timing Diagram .................................................. .
3-ClK
DRAM
Controller Schematic ........
~
...................................................... .
3-ClK
DRAM
Controller Cycles ..................................................................... .
Timing Waveforms (Read
Cycle) ...................................................... , ............ .
Timing Waveforms (Write
Cycle) ................................................................... .
Avoiding Data Bus Contention ...................................................................... .
Tap
Delay Line ............................................................................................... .
Refresh Request Generation ..................................................
, ...................... .
Cache Memory
System ................................................................................. .
Fully Associative Cache Organization ................................................ : .......... .
Direct Mapped Cache Organization .............................................
, ................ .
Two-Way
Set Associative Cache Organization ............................................. .
Stale Data Problem ........................................................................................ .
Bus Watching ................................................................................................. .
Hardware Transparency ................................................................................ .
Non-Cacheable Memory ................................................................................ .
Example of Cache Memory Organization ..................................................... .
Intel386™
DX
Microprocessor System Bus Structure ................................... .
Intel386™
DX
Microprocessor/82385 System Bus Structure ........................ .
Intel386™
DX
Microprocessor/82385 Interface ............................................. .
Direct Mapped Cache without Data Buffers .................................................. .
Direct Mapped Cache with Data Buffers ....................................................... .
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