Filter
Top Products
SA-1100 Developer’s Manual 9-37
System Control Module
9.5.7.5 Power Manager Sleep Status Register (PSSR)
PSSR contains five status flags. The software sleep status flag is set when sleep mode is entered as
a result of the force sleep (FS) control bit being set by the CPU. The battery fault status bit is set
any time the BATT_FAULT pin is asserted (even when the SA-1100 is already in sleep mode). The
VDD fault status bit is set only when the assertion of the VDD_FAULT pin causes sleep mode
invocation ( that is, if the force sleep bit is asserted and sleep mode is entered followed by the
assertion of the VDD_FAULT pin, the VDD fault status bit is not set). Hardware (power-on) reset
clears PSSR, but the sleep mode reset, software reset, and watchdog reset do not affect this register.
The peripheral hold and DRAM hold bits indicate that those two interfaces retain the same value as
during sleep until these bits are cleared.
The five status flags are cleared when a one is written to them. Writing zero to any status bit has no
effect. Reserved bits read as zeros and are unaffected by writes. The following table shows the
PSSR.
Bit31302928272625242322212019181716
R/W Reserved
Reset0000000000000000
Bit1514131211109876543210
R/W Reserved PH DH VFS BFS
SWS
Reset0000000000000000
Bit Name Description
0SS
Software sleep status.
0 – Chip has not been placed in sleep mode by setting the force sleep (FS) control bit since it
was last cleared by reset or by the CPU.
1– Chip was placed in sleep mode by setting the force sleep (FS) control bit.
1BFS
Battery fault status.
0 – BATT_FAULT pin has not been asserted since it was last cleared by a hardware reset or
by the CPU.
1 – BATT_FAULT pin has been asserted.
2VFS
VDD fault status.
0 – VDD_FAULT pin has not been asserted since it was last cleared by a hardware reset or
by the CPU.
1 – VDD_FAULT pin was asserted in run or idle mode and caused the chip to enter sleep
mode.
Note: This bit will not be set by the assertion of VDD_FAULT while the SA-1100 is in sleep
mode.