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SA-1100 Developer’s Manual 11-85
Peripheral Control Module
The status registers contain bits that signal CRC, overrun, underrun, and receiver abort errors, and
the transmit FIFO service request, receive FIFO service request, and end-of-frame conditions. Each
of these hardware-detected events signals an interrupt request to the interrupt controller. The status
registers also contains flags for transmitter busy, receiver synchronized, receive FIFO not empty,
transmit FIFO not full, and receive transition detect (no interrupt generated).
11.9.3 SDLC Control Register 0
SDLC control register 0 (SDCR0) contains 8 bit fields that control various functions within the SDLC.
11.9.3.1 SDLC/UART Select (SUS)
The SDLC/UART select (SUS) bit is used to select whether serial port 1 is used for SDLC or
UART operation. When SUS=0, SDLC operation is selected. The receiver and transmitter logic is
then enabled individually by programming the transmitter and receiver enable bits (TXE, RXE).
When SUS=0 and TXE=0, control of the transmit pin (TXD1) is given to the PPC unit; when
SUS=0 and RXE=0, control of the receive pin (RXD1) is given to the PPC unit. When SUS=1,
UART operation is selected and the state of all remaining SDLC register bits is ignored (remaining
unchanged) and control of the TXD1 and RXD1 pins is given to the UART. See the Section 11.9,
“Serial Port 1 – SDLC/UART” on page 11-78 for a description of the programming and operation
of serial port 1 as a UART. SUS, TXE, and RXE are the only bits within the control register that are
reset placing serial port 1 into SDLC mode while disabling the transmitter and receiver.
The user also has the ability to take control of two GPIO pins and use them for UART serial
transmission while the SDLC makes use of serial port 1’s transmit and receive pins to allow both
units to be used at the same time. The peripheral pin control (PPC) unit can be programmed to
connect the UART’s transmit and receive lines to GPIO pins 14 and 15. When the UART pin
reassignment (UPR) bit is set in the PPC pin assignment register (PPAR), the UART transmits using
the GPIO<14> pin and receives using the GPIO<15> pin. The SUS bit is ignored in this case and
serial port 1 operation defaults to SDLC mode. Note that the user must set bits 14 and 15 in the GPIO
alternate function register (GAFR), and set bit 14 and clear bit 15 in the GPIO pin direction register
(GPDR). See the “Peripheral Pin Controller (PPC)” on page 11-184 for a description of how to
program the PPC and the Section 9.1, “General-Purpose I/O” on page 9-1 for a description of how to
program the GPIO unit for this mode of operation.
11.9.3.2 Single/Double Flag Select (SDF)
The single/double flag select (SDF) bit is used to select whether one or two flags (01111110) are
transmitted at the start of each frame. When SDF=0, the transmit logic uses one flag. When
SDF=1, the transmit logic uses two flags. Note that SDF does not affect the number of flags that
are transmitted at the end each frame (one flag is always used). Normally, when back-to-back
transmissions are made, only one flag is inserted between the two frames (one flag serves as both
the frame’s start and end flag). However, when SDF=1, two flags are inserted between each frame.
SDF does not affect SDLC receive operation.
11.9.3.3 Loopback Mode (LBM)
The loopback mode (LBM) bit is used to enable and disable the ability of the SDLC transmit and
receive logic to communicate. When LBM=0, the SDLC operates normally. The transmit and receive
data paths are independent and communicate via their respective pins. When LBM=1, the output of
the transmit serial shifter is directly connected to the input of the receive serial shifter internally, and
control of the TXD1 and RXD1 pins are given to the peripheral pin control (PPC) unit.