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9-16 SA-1100
Developer’s Manual
System Control Module
9.2.1.5 Interrupt Controller Control Register (ICCR)
The interrupt controller control register (ICCR) contains a single control bit, the disable idle mask
bit (DIM). When set, this bit inhibits the idle mode operation where the output of the ICMR is
OR’ed to all ones. If this bit is set, then the interrupts that are capable of bringing the SA-1100 out
of idle mode are defined by the contents of the ICMR. The following table shows the location of all
interrupt level bits in the ICCR.
Bit31302928272625242322212019181716
R/W Reserved
Reset0000000000000000
Bit1514131211109876543210
R/W Reserved DIM
Reset0000000000000000
Bit Name Description
{0} DIM
Disable idle mask.
0 – All enabled interrupts will bring the SA-1100 out of idle mode.
1 – Only enabled and unmasked (as defined in the ICMR) will bring the SA-1100 out of
idle mode. This bit is cleared during all resets.
1..31 —
Reserved.