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9-28 SA-1100
Developer’s Manual
System Control Module
9.5.3.3 The Sleep Shutdown Sequence
The sleep state machine begins the shutdown sequence. This sequence consists of three steps.
• In the first step, the following actions occur:
a. Power manager switches the GPIO output pins to their sleep state. This sleep state is
programmed in advance by loading the power manager GPIO sleep state register (PGSR)
into the GPIO output data register. (See the Section 9.1, “General-Purpose I/O” on
page 9-1.)
b. The DRAMs are placed into self-refresh mode. The memory controller finishes whatever
memory operation might be in progress and then drives the RAS<3:0> and CAS<3:0>
pins low.
c. If the sleep sequence was entered due to the assertion of VDD_FAULT or BATT_FAULT,
the possible wake-up sources are reset from what was programmed by software to their
"fault state". The fault state is to allow a transition only on GP<0> and GP<1> to act as a
wake-up event.
• In the second step of sleep shutdown, the following actions occur:
a. All potential wake-up sources are cleared. This involves clearing all the GPIO edge detect
status bits and clearing the RTC alarm interrupt bit. These bits are cleared to prevent latent
status bits from causing an immediate wake-up. This functionality is provided to cover the
situation of entering sleep due to a power fault because the CPU does not have the ability
to prepare for the entry into sleep.
b. An internal reset is applied to the SA-1100. All units are reset and the RESET_OUT pin is
asserted.
• In the third step of sleep shutdown, the following actions occur:
a. The 3.686-MHz oscillator is stopped. This action is dependent on the state of the
oscillator power-down enable bit (OPDE) in the power manager configuration register
(PCFR). If this bit is set, then the oscillator is stopped during sleep, resulting in greater
power savings. If the bit is cleared (the power-on reset state), then the oscillator continues
to run during sleep and results in a faster wake-up sequence.
b. The PWR_EN pin is negated. The external system must respond to this negation by
disabling the VDDI power supply. In contrast to the SA-110, the SA-1100 systems are not
required to drive VDDI to zero volts in sleep. However, the power supply should be
disabled to prevent power consumption.
Each step in the sleep shutdown sequence takes one cycle of the 32.768-kHz clock
(~30 microseconds).
9.5.3.4 During Sleep Mode
During sleep mode, the SA-1100 watches for preprogrammed wake-up events. These events are
either programmed by the CPU prior to setting the force sleep bit or by the power manager when a
fault condition is detected.
9.5.3.5 The Sleep Wake-Up Sequence
When a valid wake-up event is detected and there is no BATT_FAULT, the SA-1100 begins a
wake-up sequence. If BATT_FAULT is asserted, then the wake-up event is ignored. VDD_FAULT
is always ignored at this time because the VDDI supply is disabled at this time. The wake-up
sequence occurs in three steps.