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SA-1100 Developer’s Manual 6-5
Caches, Write Buffer, and Read Buffer
6.2.4.1 Enabling the Dcaches
To enable the Dcaches, make sure that the MMU is enabled first by setting bit 0 in the control
register, then enable the Dcaches by setting bit 2 in the control register. The MMU and Dcaches can
be enabled simultaneously with a single control register write.
6.2.4.2 Disabling the Dcaches
To disable the Dcache, clear bit 2 in the control register.
6.3 Write Buffer (WB)
The SA-1100 write buffer is used to improve system performance by buffering up to 8 blocks of
data of 1 to 16 bytes, at independent addresses. It can be enabled or disabled via the W bit (bit 3) in
the SA-1100 control register. The buffer is disabled and all entries are marked empty following
reset. Operation of the write buffer is further controlled by the cacheable or C bit and the
bufferable or B bit, which are stored in the memory-management page tables. For this reason, in
order to use the write buffer, the MMU must be enabled. The two functions can be enabled
simultaneously with a single write to the control register. For a write to use the write buffer, both
the W bit in the control register and the B bit in the corresponding page table must be set. It is not
possible to abort buffered writes externally. Stores will not merge with other data at the same line
address in the write buffer with the exception of store multiples, which do merge.
6.3.1 Bufferable Bit
This bit controls whether a write operation may use the write buffer. Typically, main memory is
bufferable and I/O space unbufferable.
6.3.2 Write Buffer Operation
When the CPU performs a store, the Dcaches are first checked. If one of the Dcaches hits on the
store and the protection for the location and mode of the store allows the write, then the write
completes in the Dcaches and the write buffer is not used. If the location misses in the Dcaches,
then the translation entry for that address is inspected and the state of the B and C bits determines
which of the three following actions are performed. If the write buffer is disabled via the SA-1100
control register, writes are treated as if the B bit is a zero.
6.3.2.1 Writes to a Bufferable and Cacheable Location (B=1,C=1)
If the write buffer is enabled and the processor performs a write to a bufferable and cacheable
location, and the data is in one of the caches, then the data is written to that cache, and the cache
line is marked dirty. If a write to a bufferable area misses in both data caches, the data is placed in
the write buffer and the CPU continues execution. The write buffer performs the external write
sometime later. If a write is performed and the write buffer is full, then the processor is stalled until
there is sufficient space in the buffer. No write buffer merging is allowed in the SA-1100 except
during store multiples.