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SA-1100 Developer’s Manual 11-117
Peripheral Control Module
11.10.8 HSSP Control Register 2
The HSSP control register 2 (HSCR2) contains two bit-fields that control the polarity of the
transmit and receive data pins. Note that unlike the rest of the HSSP’s registers, its bits are located
in byte 2 of the addressed word (bits 23..16). Word reads or writes should be used to access this
register. Also note that this register resides within the PPC’s address space.
11.10.8.1 Transmit Pin Polarity Select (TXP)
The transmit pin polarity select (TXP) bit is used to select whether data output to the ICP’s transmit
pin (TXD2) is true or complemented. When TXP=0, data output from the UART (low-speed
mode), HSSP (high-speed mode), or PPC (GPIO output mode) is inverted first before being output
to the TXD2 pin. When TXP=1, data output from either the UART, HSSP, or PPC to the TXD2 pin
is true or noninverted. TXP is initialized to 1 following reset such that output pin data defaults to
true data.
Note that TXP affects the TXD2 pin during all modes of operation including HSSP, UART, and
PCC. The user should ensure that this bit is properly programmed when using serial port 2 for high-
or low-speed IrDA, normal UART, or GPIO operation. Note that for GPIO mode, the user needs to
configure TXP only when the pin is to be used as an output (PPDR<14>=1). When used as a GPIO
input, TXP has no effect on the state of TXD2. See the Peripheral Pin Controller chapter.
Additionally, the user must ensure that the PPC sleep state direction bit for TXD2 is inverted from
its normal value, if TXP=0 indicating inverted data. Thus if the user wishes to make TXD2 an
output in sleep mode, but TXP=0 indicating the output is inverted, the PPC should be programmed
such that PSDR<14>=1. Likewise, if TXP=0 and the user wishes to make TXD2 an input in sleep
mode, the PPC should be programmed such that PSDR<14>=0. If TXP=1 indicating true data,
PSDR should be programmed normally.
11.10.8.2 Receive Pin Polarity Select (RXP)
The receive pin polarity select (RXP) bit is used to select whether data input to the ICP’s receive
pin (RXD2) is viewed by the ICP as true or complemented. When RXP=0, data input from the
RXD2 pin is first inverted before being sent to either the UART (low-speed mode), HSSP
(high-speed mode), or PPC (GPIO input mode). When RXP=1, data input from the RXD2 pin is
treated as true data and is not inverted before being sent to either the UART, HSSP, or PPC. RXP is
initialized to 1 following reset such that input pin data defaults to true data.
Note that RXP affects the RXD2 pin during all modes of operation including HSSP, UART, and
PCC. The user should ensure that this bit is properly programmed when using serial port 2 for high-
or low-speed IrDA, normal UART, or GPIO operation. Note that for GPIO mode, the user needs to
configure RXP only when the pin is to be used as an input (PPDR<15>=0). When used as a GPIO
output, RXP has no effect on the state of RXD2.
Also note that, unlike the TXP bit, RXP has no effect on the PPC sleep state direction bit for
RXD2. PSDR<15> should be programmed normally.