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11-170 SA-1100
Developer’s Manual
Peripheral Control Module
Figure 11-35 shows the Texas Instruments* synchronous serial frame format for a single
transmitted frame and when back-to-back frames are transmitted. In this mode, SCLK and SFRM
are forced low, and the transmit data line SA-1100. Once the bottom entry of the transmit FIFO
contains data, SFRM is pulsed high for one SCLK period and the value to be transmitted is
transferred from the transmit FIFO to the transmit logic’s serial shift register. On the next rising
edge of SCLK, the MSB of the 4- to 16-bit data frame is shifted to the TXD4 pin. Likewise, the
MSB of the received data is shifted onto the RXD4 pin by the off-chip serial slave device. Both the
SSP and the off-chip serial slave device then latch each data bit into their serial shifter on the
falling edge of each SCLK. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SCLK after the LSB has been latched. Note that the transmit pin
retains the last value it transmits (the value of bit <0>, when the frame completes and the SSP
enters idle mode). If the SSP is disabled or a reset occurs, the transmit pin is reset to zero.
Figure 11-35. Texas Instruments
*
Synchronous Serial Frame Format
.
SCLK
...
SFRM
...
TXD4 Bit<N> Bit<N..1> ... Bit<1> Bit<0>
RXD4 Bit<N> Bit<N..1> ... Bit<1> Bit<0>
MSB 4 to 16 Bits LSB
Single Transfer
SCLK
... ...
SFRM
... ...
TX/RX Bit<0> Bit<N> Bit<N..1> ... Bit<1> Bit<0> Bit<N> Bit<N..1> ... Bit<1> Bit<0>
Continuous Transfers