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9-8 SA-1100
Developer’s Manual
System Control Module
9.1.1.6 GPIO Alternate Function Register (GAFR)
The GPIO alternate function register (GAFR) contains 28 control bits that correspond to the 28
GPIO port pins. When the processor sets a bit in the GAFR, the corresponding GPIO pin is
switched over to that pin’s alternate function. See the following section for details on alternate
functions. This register is cleared to all zeros on all reset conditions.
Bit31302928272625242322212019181716
R/W Reserved AF27 AF26 AF25 AF24 AF23 AF22 AF21 AF20 AF19 AF18 AF17 AF16
Reset0000000000000000
Bit1514131211109876543210
R/W AF15 AF14 AF13 AF12 AF11 AF10 AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0
Reset0000000000000000
Bit Name Description
{n} AF{n}
GPIO alternate function bits (where n = 0 through 27).
A bit set in this register indicates that the corresponding GPIO pin is to be used for its
alternate function. A zero in this register indicates that the corresponding GPIO pin is to
be used for its normal GPIO function.
31..28 — Reserved.