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SA-1100 Developer’s Manual 9-23
System Control Module
9.4.4 OS Timer Status Register (OSSR)
This status register contains status bits indicating whether a match has occurred on any of the four
match registers. These bits are set when the event occurs (following the rising edge of the
3.6864-MHz clock) and cleared by writing a one to the proper bit position. Writing zeros to this
register has no effect. All reserved bits read as zeros and are unaffected by writes; a question mark
indicates that the value is unknown at reset.
Bit31302928272625242322212019181716
R/W Reserved
Reset0000000000000000
Bit1514131211109876543210
R/W Reserved M3 M2 M1 M0
Reset000000000000????
Bit Name Description
0M0
Match status channel 0.
0 – OS timer match register<0> has not matched the OS timer counter since the last
clear.
1 – OS timer match register<0> has matched the OS timer counter.
1M1
Match status channel 1.
0 – OS timer match register<1> has not matched the OS timer counter since the last
clear.
1 – OS timer match register<1> has matched the OS timer counter.
2M2
Match status channel 2.
0 – OS timer match register<2> has not matched the OS timer counter since the last
clear.
1 – OS timer match register<2> has matched the OS timer counter.
3M3
Match status channel 3.
0 – OS timer match register<3> has not matched the OS timer counter since the last
clear.
1 – OS timer match register<3> has matched the OS timer counter.
31..4 — Reserved.