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SA-1100 Developer’s Manual 11-77
Peripheral Control Module
11.8.13.6 Reset Interrupt Request (RSTIR)
The reset interrupt request register will be set if the REM bit in the UDC control register is cleared
and the host issues a reset. When the host issues a reset, the entire UDC is reset. The RSTIR bit
retains its state so software can determine that the design was reset.
Address: 0h 8000 0030 UDCSR Read/Write (Clear)
Bit76543210
Res. RSTIR RESIR SUSIR TIR RIR EIR
Reset00000000
Bit Name Description
0EIR
Endpoint 0 interrupt request (read/write clear).
1 – Endpoint 0 needs service.
1RIR
Receive interrupt request (read/write clear).
1 – Receive endpoint (1) needs service.
2 TIR
Transmit interrupt request (read/write clear).
1 – Transmit endpoint (2) needs service.
3SUSIR
Suspend interrupt request (read/write clear).
1 – UDC received suspend signalling from the host.
4 RESIR
Resume interrupt request (read/write clear).
1 – UDC received resume signalling from the host.
5RSTIR
Reset interrupt request (read/write clear).
1 – UDC was reset by the host.
7..6 —
Reserved.
Always reads zero.