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SA-1100 Developer’s Manual 9-27
System Control Module
9.5.2.2 Exiting Idle Mode
Any enabled interrupt from the system unit or peripheral unit will cause a transition from idle mode
back to run mode. Note that the interrupt controller (ICMR) mask register is ignored during idle
mode, meaning that an interrupt does not need to be unmasked to bring the SA-1100 out of idle.
When an interrupt occurs, the CPU clocks are reactivated, the wait for interrupt instruction is
completed, and run program flow resumes.
A transition from idle to run mode can also occur by asserting the nRESET pin or if OSMR<3> is
configured as a watchdog and a match occurs that causes the assertion of reset. Since the watchdog
timer (if enabled) is functional during idle, care must be taken to set the watchdog match register
far enough in advance to ensure that another interrupt is guaranteed to bring the SA-1100 out of
idle before the watchdog reset occurs. It is recommended that either an RTC alarm or another OS
timer channel be used for this purpose.
When in idle mode, if the BATT_FAULT and/or VDD_FAULT pins are asserted, the SA-1100
enters sleep mode.
9.5.3 Sleep Mode
Sleep mode offers the greatest power savings to the user and consequently the lowest level of
available functionality. In the transition from run or idle to sleep mode, the SA-1100 performs an
orderly shutdown of on-chip activity, applies an internal reset to the processor, and then negates the
PWR_EN pin indicating to the external system that the VDDI (1.5-V supply) should be driven to
zero volts. Internally, this switches off the power to the majority of the processor at this time. (The
VDDX I/O voltage supply must remain powered during sleep.) Running off the 32.768-kHz crystal
oscillator, the sleep state machine watches for a preprogrammed wake-up event to occur, after
which it asserts PWR_EN (to reestablish the VDDI power supply), and steps through an orderly
wake-up sequence. When the power supply and clocks are stable, the power manager brings the
SA-1100 out of reset. Status bits in the reset controller status register (RCSR) may be read to
indicate to software that the reset was due to sleep mode.
9.5.3.1 CPU Preparation for Sleep Mode
In preparation for sleep mode, software should initialize the power manager GPIO sleep state
register (PGSR) and the power manager wake-up enable register (PWER). Also, the GPIO
falling-edge detect and GPIO rising-edge detect enable registers (GFER and GRER) should be
written with the appropriate values. The OPDE bit in the power manager configuration register
(PCFR) should also be programmed with the desired value.
9.5.3.2 Events Causing Entry into Sleep Mode
Sleep mode can be entered in one of two ways: via software or a power supply fault. Entry into
sleep mode via software is accomplished by setting the force sleep bit in the power manager
control register (PMCR). This bit is set by software and cleared by hardware during sleep. When
the SA-1100 wakes up from sleep, this bit is already cleared.
Entry into sleep via a power supply fault is caused by the assertion of either the VDD_FAULT or
BATT_FAULT pins. The VDD_FAULT pin should be used to indicate that the main power supply
is out of regulation. The BATT_FAULT pin should be used to indicate that the battery has been
removed or is low. These pins have identical operation for the purpose of entering sleep mode.
They have different implications during the wake-up sequence as described in the following
section.