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5-4 SA-1100
Developer’s Manual
Coprocessors
5.2.3 Register 2 – Translation Table Base
Register 2 is a read/write register that holds the base of the currently active level 1 page table. Bits
<13:0> are undefined on read, ignored on write.
5.2.4 Register 3 – Domain Access Control
Register 3 is a read/write register that holds the current access control for domains 0 to 15. Refer to
the ARM Architecture Reference for a description of the domain structure
5.2.5 Register 4 – RESERVED
Register 4 is reserved. Accessing this register yields unpredictable results.
5.2.6 Register 5 – Fault Status
Reading register 5 returns the current contents of the fault status register (FSR). The FSR is written
when a data memory fault occurs or can be written by an MCR to the FSR. It is not updated for a
prefetch fault. See Chapter 7, “Memory-Management Unit (MMU)” for more details. Bits
<31:10> are undefined on read, ignored on write. Bit 9 is set when a data breakpoint is taken and
can be cleared by an MCR operation. Bit 8 is ignored on write and is always returned as zero.
Refer to the ARM Architecture Reference for a description of the domain and status fields.
5.2.7 Register 6 – Fault Address
Reading register 6 returns the current contents of the fault address register (FAR). The FAR is
written when a data memory fault occurs with the virtual address of the data fault or can be written
by an MCR to the FAR.
0131431
Translation Table Base
012345678910111213141516171819202122232425262728293031
0123456789101112131415
0 Domain Status
03478
9
31
D
10
031
Fault Virtual Address