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SA-1100 Developer’s Manual 10-25
Memory and PCMCIA Control Module
10.5 General Memory BUS Timing
This section explains the boundary cases between DRAM, static, and refresh operations.
10.5.1 Static Access Followed by a DRAM Access
With a static memory access, nWE is deasserted 1 memory clock cycle prior to the deassertion of
nCS. Then memory control will wait 2*RRR memory clock cycles (or 1, whichever is greater)
before the assertion of nRAS for a DRAM access.
The SA-1100 always drives the data bus except while doing a read cycle (or while the alternate
master mode is active). The delay from nOE asserted to data bus high-Z is approximately 0 ns.
When nOE is deasserted, the data bus drives the same data that was already on the bus.
10.5.2 DRAM Access Followed by a Static Access
After a DRAM read cycle, the memory controller will wait TRP+1 memory cycles (or 2,
whichever is greater) before nCS is asserted for a static memory access. nWE will be asserted 2
memory clock cycles after that for a total of TRP+3 memory clock cycles. For a static memory
write after a DRAM write cycle, nWE will be asserted 3 memory clock cycles after nRAS is
deasserted.
When nOE and nRAS are deasserted at the end of a DRAM ready cycle, the SA-1100 nCS<x> and
nOE may be asserted for a static memory read, at which time the SA-1100 will stop driving in 0 ns.
If the subsequent access is a static memory write, new data will be driven out TRP+1.5 memory
clock cycles after the deassertion of nRAS and nOE. The minimum time between the end of a
DRAM refresh cycle and nWE asserted is 3 memory clock cycles.
10.5.3 DRAM Access Followed by a Refresh Operation
At the end of a DRAM read/write cycle, nCAS will go high 1/2 to 1 memory clock cycles before
nRAS goes high. For a subsequent refresh cycle, nCAS will go high TRP+1 memory clock cycles
after the nRAS goes high. After that, nRAS will go high 2 memory clock cycles. In this case, TRP
is used to hold off nCAS rather than just nRAS. There is no overlap (pipelining) between
successive memory accesses.