Filter
Top Products
SA-1100 Developer’s Manual 11-97
Peripheral Control Module
which indicates that the address, control, and data fields did not add up to an even multiple of 8
bits. When an abort is received, the current data byte within the serial shifter is discarded, the least
recent byte (the oldest of the two bytes) of data in the temporary FIFO is moved to the receive
FIFO (the other byte is discarded), and the EOF tag is set in the FIFO entry that corresponds to the
last piece of data that was received before the frame was aborted. The receiver then enters hunt
mode, searching for a flag. When the RAB bit is set, an interrupt request is made unless the
receiver abort enable (RAE) bit is cleared.
11.9.8.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable
interrupt)
The transmit FIFO service request flag (TFS) is a read-only bit that is set when the transmit FIFO is
nearly empty and requires service to prevent an underrun. TFS is set whenever the transmit FIFO
has four or fewer entries of valid data (half-full or less), and is cleared when it has five or more
entries of valid data. When the TFS bit is set, an interrupt request is made unless the transmit FIFO
interrupt request enable (TIE) bit is cleared. The state of TFS is also sent to the DMA controller,
and can be used to signal a DMA service request. Note that TIM has no effect on the generation of
the DMA service request. After the DMA or CPU fills the FIFO such that five or more locations
are filled within the transmit FIFO, the TFS flag (and the service request and/or interrupt) is
automatically cleared.
11.9.8.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable
interrupt)
The receive FIFO service request flag (RFS) is a read-only bit that is set when the receive FIFO is
nearly filled and requires service to prevent an overrun. The amount of data that causes RFS to be
set is nondeterministic. However, the range in which RFS will be set is guaranteed. RFS is set at
some point when the receive FIFO is one- to two-thirds full (or more). The UART’s FIFOs are
self-timed to reduce cost and save power. As a result, the depth at which the receive FIFO service
request is generated is variable. This is the reason the receive FIFO is twelve entries deep instead of
eight like the transmit FIFO. At which entry in the FIFO the request is actually triggered is
dependent on IC process, operating temperature, and so on. The receive FIFO is designed to signal
the RFS bit to be set when it contains eight entries of valid data. However, because of the
variability of the self-timed logic, RFS may also be set when seven, six, or five entries of valid data
are present within the FIFO. Likewise, under normal circumstances, RFS is cleared when the
receive FIFO has seven remaining entries of valid data. However, again due to variations, RFS may
be cleared when six or five entries of data remain.
When the RFS bit is set, a DMA service request is made. An interrupt request is also made unless
the receive FIFO interrupt request enable (RIE) bit is cleared. Even though more than four entries
of data may exist within the receive FIFO, the user must configure the DMA burst size to four
words. If programmed I/O is used to service the receive FIFO, a maximum of 4 words may be
removed without checking if data is valid. After this point, the receive FIFO not empty (RNE) flag
must be polled before each read to see if more data remains. After the DMA or CPU empties the
FIFO such that five or more empty locations are available within the receive FIFO, the RFS flag (as
well as the DMA and interrupt request) is automatically cleared.