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SA-1100 Developer’s Manual ix
11.8.3.1UDC Disable (UDD)............................................................. 11-64
11.8.3.2 UDC Active (UDA) .............................................................. 11-64
11.8.3.3Bit 2 Reserved ..................................................................... 11-64
11.8.3.4Endpoint 0 Interrupt Mask (EIM).......................................... 11-64
11.8.3.5Receive Interrupt Mask (RIM)............................................. 11-64
11.8.3.6Transmit Interrupt Mask (TIM) ............................................ 11-64
11.8.3.7Suspend/Resume Interrupt Mask (SRM)............................. 11-65
11.8.3.8Reset Interrupt Mask (REM)................................................ 11-65
11.8.4 UDC Address Register ..................................................................... 11-66
11.8.5 UDC OUT Max Packet Register ....................................................... 11-66
11.8.6 UDC IN Max Packet Register ........................................................... 11-67
11.8.7 UDC Endpoint 0 Control/Status Register.......................................... 11-68
11.8.7.1OUT Packet Ready (OPR)................................................... 11-68
11.8.7.2IN Packet Ready (IPR) ........................................................ 11-68
11.8.7.3Sent Stall (SST)................................................................... 11-68
11.8.7.4Force Stall (FST) ................................................................. 11-68
11.8.7.5Data End (DE) ..................................................................... 11-68
11.8.7.6Setup End (SE).................................................................... 11-68
11.8.7.7Serviced OPR (SO) ............................................................. 11-68
11.8.7.8Serviced Setup End (SSE) .................................................. 11-69
11.8.8 UDC Endpoint 1 Control/Status Register.......................................... 11-70
11.8.8.1Receive FIFO Service (RFS)............................................... 11-70
11.8.8.2Receive Packet Complete (RPC) ........................................ 11-70
11.8.8.3Receive Packet Error (RPE)................................................ 11-70
11.8.8.4Sent Stall (SST)................................................................... 11-70
11.8.8.5Force Stall (FST) ................................................................. 11-70
11.8.8.6Receive FIFO Not Empty (RNE).......................................... 11-70
11.8.8.7Bits 7..6 Reserved ............................................................... 11-71
11.8.9 UDC Endpoint 2 Control/Status Register.......................................... 11-72
11.8.9.1Transmit FIFO Service (TFS) .............................................. 11-72
11.8.9.2Transmit Packet Complete (TPC)........................................ 11-72
11.8.9.3 Transmit Packet Error (TPE) .............................................. 11-72
11.8.9.4Transmit Underrun (TUR).................................................... 11-72
11.8.9.5Sent STALL (SST)............................................................... 11-72
11.8.9.6Force STALL (FST) ............................................................. 11-72
11.8.9.7Bits 7..6 Reserved ............................................................... 11-73
11.8.10 UDC Endpoint 0 Data Register......................................................... 11-74
11.8.11 UDC Endpoint 0 Write Count Register ............................................. 11-74
11.8.12 UDC Data Register........................................................................... 11-75
11.8.13 UDC Status/Interrupt Register .......................................................... 11-76
11.8.13.1Endpoint 0 Interrupt Request (EIR) ................................... 11-76
11.8.13.2Receive Interrupt Request (RIR) ....................................... 11-76
11.8.13.3Transmit Interrupt Request (TIR)....................................... 11-76
11.8.13.4Suspend Interrupt Request (SUSIR) ................................. 11-76
11.8.13.5Resume Interrupt Request (RESIR) .................................. 11-76
11.8.13.6 Reset Interrupt Request (RSTIR) ..................................... 11-77
11.8.14 UDC Register Locations ................................................................... 11-78
11.9 Serial Port 1 – SDLC/UART........................................................................... 11-78
11.9.1 SDLC Operation ............................................................................... 11-79
11.9.1.1Bit Encoding......................................................................... 11-79
11.9.1.2Frame Format...................................................................... 11-80
11.9.1.3Address Field....................................................................... 11-80
11.9.1.4Control Field ........................................................................ 11-80