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11-70 SA-1100
Developer’s Manual
Peripheral Control Module
11.8.8 UDC Endpoint 1 Control/Status Register
The UDC endpoint 1 control/status register contains 6 bits that are used to operate endpoint 1
(OUT endpoint).
11.8.8.1 Receive FIFO Service (RFS)
The receive FIFO service bit will be set if the receive FIFO has between 8 and 12 or more bytes
(out of 20) in it. Because the FIFOs are asynchronous, the exact threshold cannot be determined,
but is guaranteed to be in this range. This signal is also used as a DMA request signal to trigger the
DMA unit to service the FIFO.
11.8.8.2 Receive Packet Complete (RPC)
The receive packet complete bit gets set by the UDC when an OUT packet has been received.
When this bit is set the RIR bit in the UDC status/interrupt register will be set if receive interrupts
are enabled. This bit can be used to validate the other status/error bits in the endpoint 1
control/status register. The RPC bit gets cleared by writing a one to it. The UDC will issue NAK
handshakes to all OUT tokens while this bit is set.
11.8.8.3 Receive Packet Error (RPE)
The receive packet error bit will be set if a CRC, bit stuffing, or FIFO overrun error occurs. It is
only valid if the RPC bit (1) is set and gets cleared when the RPC bit gets cleared.
11.8.8.4 Sent Stall (SST)
The sent stall bit is set by the UDC when it must abort the current transfer by issuing a STALL
handshake due to a protocol violation (the host sends more data than the maximum packet size).
The CPU clears this bit by writing a one to it.
11.8.8.5 Force Stall (FST)
The force stall bit can be set by the UDC to force the UDC to issue a STALL handshake to all OUT
tokens. STALL handshakes will continue to be sent until the CPU clears this bit. The sent stall bit
(3) will be set when the STALL state is actually entered (this may be delayed if the UDC is active
when the FST bit is set), and the STALL state will not be exited until both the FST and SST bits are
cleared.
11.8.8.6 Receive FIFO Not Empty (RNE)
The receive FIFO not empty bit indicates that there is unread data in the receive FIFO. This bit
must be polled when the RPC bit is set to determine if there is any data in the FIFO that DMA did
not read. The receive FIFO must continue to be read until this bit clears or data will be lost.