Filter
Top Products
6-2 SA-1100
Developer’s Manual
Caches, Write Buffer, and Read Buffer
6.1.3 Icache Enable/Disable and Reset
The Icache is automatically disabled and flushed on the assertion of nRESET. Once enabled,
cacheable read accesses cause lines to be placed in the cache. If the Icache is subsequently
disabled, no new lines are placed in the cache, but the cache is still searched and if the data is
found, it will be used by the processor. If the data in the cache must not be used, then the cache
must be flushed.
6.1.3.1 Enabling the Icache
To enable the Icache, set bit 12 in the control register. The MMU and Icache may be enabled
simultaneously with a single control register write.
6.1.3.2 Disabling the Icache
To disable the Icache, clear bit 12 in the control register.
6.2 Data Caches (Dcaches)
The SA-1100 contains two logically separate data caches: the main data cache and the mini data
cache (or minicache). The main data cache, an 8 Kbyte write-back Dcache, has 256 lines of 32
bytes (8words) in a 32-way set-associative organization. It is intended for use during most data
accesses. This cache allocates on loads to spaces marked B=1 and C=1. Replacements in the main
data cache are selected according to a set of round-robin pointers. At reset, the pointer in each
block of the Dcache points to way zero of each 32-way block. As lines are allocated, the pointers
are incremented to the next way of the set. After way 31 is allocated, the next linefill replaces (and
copies back to memory, if dirty) the data in way zero. The minicache is a 512-byte write-back
cache. It has 16 lines of 32 bytes (8 words) in a two-way set-associative organization and provides
an alternate caching structure for dealing with large data structures that could thrash the main data
cache. This cache allocates on loads to spaces marked B=0 and C=1. Replacements in the
minicache use the same round-robin pointer mechanism as in the main data cache. However, since
this cache is only two-way set-associative, the replacement algorithm reduces to a simple
least-recently-used (LRU) mechanism.
The Dcaches are accessed in parallel and the design ensures that a particular line entry will exist in
only one of the two at any time. Both Dcaches use the virtual address generated by the processor
and allocate only on loads (write misses never allocate in the cache). Each line entry contains the
physical address of the line and two dirty bits. The dirty bits indicate the status of the first and the
second halves of the line. When a store hits in the Dcaches, the dirty bit associated with it is set.
When a line is evicted from the Dcaches, the dirty bits are used to decide if all, half, or none of the
line will be written back to memory using the physical address stored with the line. The Dcaches
are always reloaded a line at a time (8 words).
The Dcaches allocate only on loads and according to the settings of the B and C bits in the MMU.
If B=0 and C=1, the memory access allocates into the minicache. If B=1 and C=1, the memory
access allocates into the main data cache. The Dcaches should be flushed prior to changing the
bufferable and/or cacheable state of the page table mapping.
The main data cache and the minicache are enabled and disabled via the SA-1100 control register,
and are disabled on nRESET as well as software, sleep, and watchdog reset. The operation of the
Dcaches is further controlled by the cacheable or C bit and the bufferable or B bit stored in the