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9-38 SA-1100
Developer’s Manual
System Control Module
3DHDRAM control hold.
This bit is set upon exit from sleep mode and indicates that the RAS<3:0> and CAS<3:0>
continue to be held low and that the DRAMs are still in self-refresh mode. This bit should be
cleared by the processor (by writing a one to it) after the DRAM interface has been configured
but before any DRAM access is attempted. The RAS and CAS lines are released when this
bit is cleared. This bit is cleared on hardware reset.
4PH
Peripheral control hold.
This bit is set upon exit from sleep mode and indicates that the peripheral pins are being held in
their sleep state. This bit should be cleared by the processor (by writing a one to it) after the
peripheral interfaces have been configured but before they are actually used by the processor.
31..5 — Reserved.
Bit Name Description