Filter
Top Products
SA-1100 Developer’s Manual 11-125
Peripheral Control Module
11.10.11.6 CRC Error Status (CRE) (read-only, noninterruptible)
The CRC error flag (CRE) is set when the CRC value calculated by the receive logic does not
match the CRC value contained within the incoming serial data stream.
The receive FIFO contains three tag bits (8, 9, and 10) that are not directly readable. Whenever a
CRC error is detected, the 9th bit is set within the top entry of the receive FIFO corresponding to
the last byte of data within the frame. This tag travels along with the last piece of data from the
frame as it moves down the FIFO. Each time a data value is transferred to the bottom of the FIFO
(caused by a read of the previous value), the state of the tag bit is moved from the FIFO to the CRE
bit in the status register, indicating whether or not the frame has encountered a CRC error.
Whenever CRE is set within the bottom half of the receive FIFO, EIF is set within HSSR0, an
interrupt is signalled, and the receive FIFO DMA request is disabled. After the end/error in FIFO
(EIF) status bit is set, the user should always read HSSR1 first to check CRE before reading the
data value from HSDR because CRE corresponds to the current data byte at the bottom of the
receive FIFO and is updated each time data is removed from the FIFO.
11.10.11.7 Receiver Overrun Status (ROR) (read-only, noninterruptible)
The receiver overrun flag (ROR) is set when the receive logic attempts to place data into the
receive FIFO after it has been completely filled.
The receive FIFO contains three tag bits (8, 9, and 10) that are not directly readable. The 10th bit is
set within the top entry of the receive FIFO whenever an overrun occurs. This tag travels along
with the last “good” data value before the overflow occurred as it moves down the FIFO. Each time
a data value is transferred to the bottom of the FIFO (caused by a read of the previous value), the
state of the tag bit is moved from the FIFO to the ROR bit in the status register, indicating that the
next value in the FIFO is the last “good” piece of data before the overflow occurred. Whenever
ROR is set within the bottom eight entries of the receive FIFO, EIF is set within HSSR0, an
interrupt is signalled, and the receive FIFO DMA request is disabled. After the end/error in FIFO
(EIF) status bit is set, the user should always read HSSR1 first to check ROR before reading the
data value from HSDR because ROR corresponds to the current data byte at the bottom of the
receive FIFO and is updated each time data is removed from the FIFO.