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SA-1100 Developer’s Manual 10-15
Memory and PCMCIA Control Module
10.3.2 DRAM Timing
The DRAM nCAS timing is generated using shift registers. The rate at which these shift registers
are clocked is determined by MDCNFG:CDB2. The time at which to sample the read data is
programmable to coincide with the deassertion of nCAS or up to 3 CPU cycles later. This method
provides a way to take advantage of the EDO DRAMs while still supporting the fast-page-mode
DRAMs. A full 8-beat burst nCAS waveform is specified, and the memory interface controller
shifts the waveform shift register once every CPU clock cycle if MDCNFG:CDB2=0 and once
every 2 CPU clock cycles if MDCNFG:CDB2=1. The shifting continues until the number of nCAS
pulses have been generated that corresponds to the actual number of data words being accessed.
Registers MDCAS0, MDCAS1, and MDCAS2 contain the nCAS waveform for a full 8-beat burst
access to DRAM. To begin an access, the row address is output on DRA(11:0), which is A(21:10).
One CPU clock later (1/2 memory clock), nRAS is asserted and the nCAS waveform begins and is
shifted with each CPU clock, if MDCNFG:CDB2=0. A 1 in this shift register drives nCAS high
(deasserts) at the rising edge of the CPU clock cycle, and a 0 drives nCAS low (asserts). The
column address for the first beat of data will be valid 1 CPU cycle before nCAS transitions from
deasserted to asserted. During reads, a rising edge is detected on the nCAS waveform and input
data is latched MDCNFG:TDL cycles after the rising edge. The shift register continues to shift
until the number of nCAS pulses equals the burst size of the current transaction. For write
transactions, nRAS will be deasserted on the next rising memory clock edge after the last nCAS
rising edge (either 1 or 2 CPU clock cycles). For read transactions, nRAS will be deasserted on the
rising memory clock cycle edge that occurs either 2 or 3 CPU clock cycles after the input data is
latched. For each additional beat after the first, the column address will be updated coincident with
the deassertion of nCAS, or 1 CPU cycle later. For writes, the write data outputs will follow the
same timing as the column address. nWE and nOE, as appropriate, follow the same timing as
nRAS. After nRAS is deasserted, the timing parameter MDCNFG:TRP is used to determine the
wait before the next assertion of nRAS.
If MDCNFG:CDB2=1, the nCAS waveform will be shifted every memory clock, or every 2 CPU
cycles. The timing of the other signals remains the same relative to the nCAS waveform. For
MDCNFG:CDB2=0, there is a requirement that nCAS high and low times be programmed with a
minimum of 2 bits and the 4 least significant bits in MDCAS0 must be 1. For the
MDCNFG:CDB2=1 case, high and low nCAS pulse times may be 1 bit each and the least significant
2 bits of MDCAS0 must be 1. These requirements are necessary for the internal hardware to properly
generate addresses and write data, and for proper address and data setup times.