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SA-1100 Developer’s Manual 11-55
Peripheral Control Module
Figure 11-14. Active Mode Pixel Clock and Data Pin Timing
A4794-01
L_FCLK
(VSYNC)
L_BIAS
OE)
L_LCLK
(HSYNC)
L_PCLK
LDD[7:0],
GPIO[9:2]
Notes:
PCP - Pixel clock polarity:
0 - Pixels sampled from data pins on rising edge of pixel clock.
1 - Pixels sampled from data pins on falling edge of pixel clock.
Pixels 0 through 15 Pixels 32 through 47 Pixels 48 through 63Pixels 16 through 31
Data Pins Change
PCP = 0
Data Pins Sampled
by the Display