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11-180 SA-1100
Developer’s Manual
Peripheral Control Module
11.12.11 SSP Data Register
The SSP data register (SSDR) is 16 bits wide and corresponds to the top and bottom entries of the
transmit and receive FIFOs, respectively. When SSDR is read, the bottom entry of receive FIFO is
accessed. As data is removed by the SSP’s receive logic from the incoming data frame, it is placed
into the top entry of the receive FIFO and is transferred down an entry at a time until it reaches the
last empty location within the FIFO. Data is removed by reading SSDR, which accesses the bottom
entry of the FIFO. After SSDR is read, the bottom entry is invalidated, and all remaining values
within the FIFO automatically transfer down one location.
When SSDR is written, the topmost entry of the transmit FIFO is accessed. After a write, data is
automatically transferred down to the lowest location within the transmit FIFO, which does not
already contain valid data. Data is removed from the bottom of the FIFO one value at a time by the
transmit logic, is loaded into the transmit serial shifter, and then is serially shifted onto the TXD4
pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user should left justify data written to the
transmit FIFO. The transmit logic ignores the upper unused bits. Received data less than 16 bits is
automatically right justified in the receive buffer and unused bits are zero filled. When the SSP is
programmed for National Microwire
*
frame format, the default size for transmit data is 8 bits (the
most significant byte is ignored) and the receive data size is controlled by the programmer.
The following table shows the location of the SSP data register. Note that both FIFOs are cleared
when the SA-1100 is reset or by writing a zero to SSE (SSP disabled).
Address: 0h 8007 006C SSP Data Register: SSDR Read/Write
Bit1514131211109876543210
Bottom of Receive FIFO
Reset0000000000000000
Read Access
Bit1514131211109876543210
Top of Transmit FIFO
Reset0000000000000000
Write Access
Bit Name Description
15..0 Data
Top/bottom of transmit/receive FIFO.
Read – Bottom of receive FIFO.
Write – Top of transmit FIFO.
Note: User should left justify data when SSP programmed for a data size less than 16
bits. Top unused bits are ignored by transmit logic. Receive logic automatically right
justifies data and zero fills unused bits.