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11-114 SA-1100
Developer’s Manual
Peripheral Control Module
transmitting and receiving data at the same time; both are fully independent units. This function is
particularly useful when using the HSSP in loopback mode. See the Section 11.10.6.2, “Loopback
Mode (LBM)” on page 11-112.
11.10.6.5 Receive Enable (RXE)
The receive enable (RXE) bit is used to enable or disable HSSP receive operation. When RXE=0, the
receive logic is disabled and its clocks are turned off to conserve power. When RXE=1, the HSSP
receiver logic is enabled for IrDA reception. It is required that the user first program all other control
bits before setting RXE. If the RXE bit is cleared to zero while the HSSP is actively receiving data,
reception is stopped immediately, all data within the receive FIFO and serial input shifter is cleared,
and control of the RXD2 pin is given to the peripheral pin control (PPC) unit. Note that TXE and
RXE are the only control bits within the HSSP that are initialized when a hardware reset occurs.
Clearing RXE to zero ensures the HSSP receiver is disabled, giving control of the receive pin to the
PPC unit, which configures RXD2 as an input following a reset of the SA-1100. Note that RXE is
ignored when ITR=0, which enables UART operation. Also note that even though the IrDA standard
permits only half-duplex operation, the HSSP does not restrict the user from transmitting and
receiving data at the same time; both are fully independent units. This function is particularly useful
when using the HSSP in loopback mode. See the Section 11.10.6.2, “Loopback Mode (LBM)” on
page 11-112.
11.10.6.6 Receive FIFO Interrupt Enable (RIE)
The receive FIFO interrupt mask (RIE) bit is used to mask or enable the receive FIFO service
request interrupt. When RIE=0, the interrupt is masked, and the state of the receive FIFO service
request (RFS) bit within HSSP status register 0 is ignored by the interrupt controller. When RIE=1,
the interrupt is enabled, and whenever RFS is set (one), an interrupt request is made to the interrupt
controller. Note that programming RIE=0 does not affect the current state of RFS or the receive
FIFO logic’s ability to set and clear RFS; it only blocks the generation of the interrupt request.
Also note that RIE does not affect generation of the receive FIFO DMA request , which is asserted
whenever RFS=1.
11.10.6.7 Transmit FIFO Interrupt Enable (TIE)
The transmit FIFO interrupt mask (TIE) bit is used to mask or enable the transmit FIFO service
request interrupt. When TIE=0, the interrupt is masked and the state of the transmit FIFO service
request (TFS) bit within HSSP status register 0 is ignored by the interrupt controller. When TIE=1,
the interrupt is enabled, and whenever TFS is set (one), an interrupt request is made to the interrupt
controller. Note that programming TIE=0 does not affect the current state of TFS or the transmit
FIFO logic’s ability to set and clear TFS; it only blocks the generation of the interrupt request.
Also note that TIE does not affect generation of the transmit FIFO DMA request, which is asserted
whenever TFS=1.
11.10.6.8 Address Match Enable (AME)
The address match enable (AME) bit is used to enable or disable the receive logic from comparing
the address programmed in the address match value (AMV) bit field to the address of all incoming
frames. When AME=1, data is stored in the receive FIFO only for those frames that have addresses
that match AMV and for any frame that contains an address containing all ones (11111111),
denoting a global address. For frames in which the address does not match, the data and CRC are
ignored and the receiver resumes hunting for a preamble. When AME=0, address values are not
compared and the data in every frame is stored in the receive FIFO.