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SA-1100 Developer’s Manual 11-47
Peripheral Control Module
11.7.11.4 AC Bias Count Status (ABC) (read/write, nonmaskable interrupt)
The ac bias count status (ABC) bit it set each time the ac bias pin (L_BIAS) transitions a particular
number of times as specified by the ac bias pin transitions per interrupt (API) field in LCCR3. If
API is programmed with a nonzero value, a counter is loaded with the value in API and is
decremented each time the L_BIAS pin reverses state. When the counter reaches zero, the ABC bit
is set, which signals an interrupt request to the interrupt controller. The counter reloads using the
value in API, but does not start to decrement again until ABC is cleared by the user.
11.7.11.5 Input FIFO Overrun Lower Panel Status (IOL) (read/write, maskable
interrupt)
The input FIFO overrun lower panel status (IOL) bit is set when the LCD’s DMA channel 2
attempts to place data into the lower panel’s input FIFO after it has been completely filled. It is
cleared by writing a one to the bit. This bit is used only in dual-panel mode (SDS=1). When this bit
is set, an interrupt request is made to the interrupt controller if it is unmasked (ERM=0).
11.7.11.6 Input FIFO Underrun Lower Panel Status (IUL) (read/write, maskable
interrupt)
The input FIFO underrun lower panel status (IUL) bit is set when the lower panel’s input FIFO is
completely empty and the LCD’s pixel unpacking logic attempts to fetch data from the FIFO. It is
cleared by writing a one to the bit. This bit is used only in dual-panel mode (SDS=1). When this bit
is set, an interrupt request is made to the interrupt controller if it is unmasked (ERM=0).
11.7.11.7 Input FIFO Overrun Upper Panel Status (IOU) (read/write, maskable
interrupt)
The input FIFO overrun upper panel status (IOU) bit is set when the LCD’s DMA channel 1
attempts to place data into the upper panel’s input FIFO after it has been completely filled. It is
cleared by writing a one to the bit. This bit is used in single-panel mode (SDS=0) and dual-panel
mode (SDS=1). When this bit is set, an interrupt request is made to the interrupt controller if it is
unmasked (ERM=0).
11.7.11.8 Input FIFO Underrun Upper Panel Status (IUU) (read/write, maskable
interrupt)
The input FIFO underrun upper panel status (IUU) bit is set when the upper panel’s input FIFO is
completely empty and the LCD’s pixel unpacking logic attempts to fetch data from the FIFO. It is
cleared by writing a one to the bit. This bit is used in single-panel mode (SDS=0) and dual-panel
mode (SDS=1). When this bit is set, an interrupt request is made to the interrupt controller if it is
unmasked (ERM=0).
11.7.11.9 Output FIFO Overrun Lower Panel Status (OOL) (read/write, maskable
interrupt)
The output FIFO overrun lower panel status (OOL) bit is set when the LCD’s dither logic attempts
to place data into the lower panel’s output FIFO after it has been completely filled. It is cleared by
writing a one to the bit. This bit is used only in dual-panel mode (SDS=1). When this bit is set, an
interrupt request is made to the interrupt controller if it is unmasked (ERM = 0).