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11-90 SA-1100
Developer’s Manual
Peripheral Control Module
11.9.4.6 Address Match Enable (AME)
The address match enable (AME) bit is used to enable or disable the receive logic from comparing
the address programmed in the address match value (AMV) bit field to the address of all incoming
frames. When AME=1, data is stored in the receive FIFO for only those frames that have
addresses that match AMV, and for any frame that contains an address that contains all ones
(11111111), denoting a global address. For frames in which the address does not match, the data
and CRC are ignored and the receiver begins to search for the next flag. When AME=0, address
values are not compared and the data in every frame is stored in the receive FIFO.
11.9.4.7 Transmit FIFO Underrun Select (TUS)
The transmit FIFO underrun select (TUS) bit is used to select what action to take as a result of a
transmit FIFO underrun and to mask or enable the transmit FIFO underrun interrupt.
When TUS=0, transmit FIFO underruns are used to signal the transmit logic that the end of the
frame has been reached. When the transmit FIFO experiences an underrun, the CRC value, which
is calculated continuously on outgoing data, is loaded to the serial shifter and transmitted, followed
by a flag. Also when TUS=0, the transmit FIFO interrupt is masked and the state of the transmit
FIFO underrun (TUR) status bit is ignored by the interrupt controller.
When TUS=1, transmit FIFO underruns are used to signal the transmit logic that the end of the
frame has not yet been reached and that the rate in which data is supplied to the transmit FIFO is
not sufficient. When the transmit FIFO experiences an underrun, ones are continuously output by
the transmitter to signal an abort condition until data is once again available within the transmit
FIFO, and the CRC value is discarded. Additionally, when TUS=1, the transmit FIFO underrun
interrupt is enabled, and whenever TUR is set (one), an interrupt request is made to the interrupt
controller. To change the state of this bit during operation, the user should fill the transmit FIFO to
ensure TUS is not written at the same time the transmit FIFO underruns. Note that programming
TUS=0 does not affect the current state of TUR or the transmit FIFO logic’s ability to set and clear
TUR; it only blocks the generation of the interrupt request.
TUS is useful for ensuring that frames are not prematurely ended due to an unexpected transmit FIFO
underrun. At the start of a frame, the user can configure TUS=1 so that any underrun signals an abort
to the off-chip receiver. Just before the end of the frame, the user can then configure TUS=0 (the last
time the transmit FIFO is filled, for example), allowing the remaining data to be output by the
transmit logic. The FIFO then underruns, causing the CRC and end flag to be transmitted.
11.9.4.8 Receiver Abort Interrupt Enable(RAE)
The receiver abort interrupt enable (RAE) bit is used to mask or enable whether or not an abort
sequence, which is detected by the receive logic, generates an interrupt to the CPU. When RAE=0,
the interrupt is masked and the state of the receiver abort status (RAS) bit is ignored by the
interrupt controller. When RAE=1, the interrupt is enabled and whenever RAS is set (one), an
interrupt request is made to the interrupt controller. Note that programming RAE=0 does not affect
the current state of RAS or the receive logic’s ability to set and clear RAS as the result of an abort
detect; it only blocks the generation of the interrupt request.