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Memory Configuration: On-Card SDRAM
KAT4000 User’s Manual 10007175-02
6-2
Caution: When removing socketed PLCC devices, always use an extraction tool designed specifically
for that task. Otherwise, you risk damaging the PLCC device.
The KAT4000 supports a redundant boot bank. This boot bank is automatically used if the
primary bank fails to boot properly. The primary and redundant banks are designated from
the local processor as well as remotely over IPMI. The watchdog timer on the MPC8548 will
be used to change the boot select direction after a watchdog expiration event.
ON-CARD SDRAM
The KAT4000 supports 512 megabytes and 1 gigabyte of 72-bit wide DDR2 SDRAM. This
interface implements eight additional bits to permit the use of Error-Correcting Code
(ECC). ECC can also be disabled for specific configurations. The SDRAM interface clock
speed is 200 MHz.
A low profile, small-outline, dual inline memory module (SO-DIMM) is installed in a 200-pin
socket to reduce board density and routing constraints. An I
2
C serial EEPROM on the SO-
DIMM provides the serial presence detects (SPD). SDRAM occupies physical addresses from
0000,0000
16
to 3FFF,FFFF
16
.
In addition to the basic SDRAM control functions, the chip provides several additional
DRAM-related functions and contains the following performance enhancing features:
• Supports page mode—minimizing SDRAM cycles on multiple transactions to the same
SDRAM page and can be configured to support up to 16 simultaneously opened pages
• Supports Error-Correcting Code (ECC) and Read-Modify-Write (RMW) in the case of
partial writes (smaller than 64-bit) to DRAM
• ECC provides single bit error correction and two bit error detection
NAND FLASH
The KAT4000 uses 512 MB or 1 GB of M-systems DiskOnChip NAND Flash, starting at physi-
cal address FC00,0000, for non-volatile RAM storage and True Flash File System (TFFS). The
DiskOnChip incorporates an embedded flash controller and memory, and features hard-
ware protection and security-enabling features, an enhanced programmable boot block
enabling eXecute In Place (XIP) functionality using 16-bit access, user-controlled One Time
Programmable (OTP) partitions, and 6-bit Error Detection Code/Error Correction Code
(EDC/ECC).
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